SPRUJ53B April 2024 – September 2024 TMS320F28P550SJ , TMS320F28P559SJ-Q1
Table 12-5 lists the memory-mapped registers for the DMA_REGS registers. All register offset addresses not listed in Table 12-5 should be considered as reserved locations and the register contents should not be modified.
| Offset | Acronym | Register Name | Write Protection | Section |
|---|---|---|---|---|
| 0h | DMACTRL | DMA Control Register | EALLOW | Go |
| 1h | DEBUGCTRL | Debug Control Register | EALLOW | Go |
| 4h | PRIORITYCTRL1 | Priority Control 1 Register | EALLOW | Go |
| 6h | PRIORITYSTAT | Priority Status Register | EALLOW | Go |
Complex bit access types are encoded to fit into small table cells. Table 12-6 shows the codes that are used for access types in this section.
| Access Type | Code | Description |
|---|---|---|
| Read Type | ||
| R | R | Read |
| R-0 | R -0 | Read Returns 0s |
| Write Type | ||
| W | W | Write |
| W1S | W 1S | Write 1 to set |
| Reset or Default Value | ||
| -n | Value after reset or the default value | |
DMACTRL is shown in Figure 12-8 and described in Table 12-7.
Return to the Summary Table.
DMA Control Register
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PRIORITYRESET | HARDRESET | |||||
| R-0h | R-0/W1S-0h | R-0/W1S-0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-2 | RESERVED | R | 0h | Reserved |
| 1 | PRIORITYRESET | R-0/W1S | 0h | The priority reset bit resets the round-robin state machine when a 1 is written. Service starts from the first enabled channel. Writes of 0 are ignored and this bit always reads back a 0. When a 1 is written to this bit, any pending burst transfer completes before resetting the channel priority machine. If CH1 is configured as a high-priority channel, and this bit is written to while CH1 is servicing a burst, both the CH1 burst and the next pending low-priority burst are completed before the state machine is reset. If CH1 is high-priority, the state machine restarts from CH2 (or the next highest enabled channel). Reset type: SYSRSn |
| 0 | HARDRESET | R-0/W1S | 0h | Writing a 1 to the hard reset bit resets the whole DMA and aborts any current access (similar to applying a device reset). Writes of 0 are ignored and this bit always reads back a 0. For a soft reset, a bit is provided for each channel to perform a gentler reset. Refer to the channel control registers. When writing to this bit, there is a one cycle delay before it takes effect. Hence, a one-cycle delay (such as a NOP instruction) is required in software before attempting to access any other DMA register. Reset type: SYSRSn |
DEBUGCTRL is shown in Figure 12-9 and described in Table 12-8.
Return to the Summary Table.
Debug Control Register
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| FREE | RESERVED | ||||||
| R/W-0h | R-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | |||||||
| R-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | FREE | R/W | 0h | Emulation Control This bit specifies the action when an emulation halt event occurs. Reset type: SYSRSn 0h (R/W) = The DMA completes the current read-write operation, then halts. 1h (R/W) = The DMA continues running during an emulation halt. |
| 14-0 | RESERVED | R | 0h | Reserved |
PRIORITYCTRL1 is shown in Figure 12-10 and described in Table 12-9.
Return to the Summary Table.
Priority Control 1 Register
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | CH1PRIORITY | ||||||
| R-0h | R/W-0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-1 | RESERVED | R | 0h | Reserved |
| 0 | CH1PRIORITY | R/W | 0h | DMA Channel 1 Priority This bit selects whether CH1 has high priority or not. The priority can only be changed when all channels are disabled. A priority reset should be performed before restarting channels after changing priority Reset type: SYSRSn 0h (R/W) = CH1 has the same priority as the other channels 1h (R/W) = CH1 has a higher priority than the other channels |
PRIORITYSTAT is shown in Figure 12-11 and described in Table 12-10.
Return to the Summary Table.
Priority Status Register
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | ACTIVESTS_SHADOW | RESERVED | ACTIVESTS | ||||
| R-0h | R-0h | R-0h | R-0h | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-7 | RESERVED | R | 0h | Reserved |
| 6-4 | ACTIVESTS_SHADOW | R | 0h | Active Channel Status Shadow These bits are only meaningful when CH1 is in high-priority mode. When CH1 is serviced, the ACTIVESTS bits are copied to the shadow bits and indicate which channel was interrupted by CH1. When CH1 service is completed, the shadow bits are copied back to the ACTIVESTS bits. If this bit field is zero or the same as the ACTIVESTS bit field, then no channel is pending due to a CH1 interrupt. When CH1 is not a higher priority channel, these bits should be ignored. Reset type: SYSRSn 0h (R/W) = No channel is active 1h (R/W) = CH 1 2h (R/W) = CH 2 3h (R/W) = CH 3 4h (R/W) = CH 4 5h (R/W) = CH 5 6h (R/W) = CH 6 7h (R/W) = Reserved |
| 3 | RESERVED | R | 0h | Reserved |
| 2-0 | ACTIVESTS | R | 0h | Active Channel Status These bits indicate which channel (if any) is currently active or performing a transfer. Reset type: SYSRSn 0h (R/W) = No channel is active 1h (R/W) = CH 1 2h (R/W) = CH 2 3h (R/W) = CH 3 4h (R/W) = CH 4 5h (R/W) = CH 5 6h (R/W) = CH 6 7h (R/W) = Reserved |