SPRUJ53B April 2024 – September 2024 TMS320F28P550SJ , TMS320F28P559SJ-Q1
Table 11-31 lists the memory-mapped registers for the XBAR_REGS registers. All register offset addresses not listed in Table 11-31 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Write Protection | Section |
---|---|---|---|---|
0h | XBARFLG1 | X-Bar Input Flag Register 1 | Go | |
2h | XBARFLG2 | X-Bar Input Flag Register 2 | Go | |
4h | XBARFLG3 | X-Bar Input Flag Register 3 | Go | |
6h | XBARFLG4 | X-Bar Input Flag Register 4 | Go | |
8h | XBARCLR1 | X-Bar Input Flag Clear Register 1 | Go | |
Ah | XBARCLR2 | X-Bar Input Flag Clear Register 2 | Go | |
Ch | XBARCLR3 | X-Bar Input Flag Clear Register 3 | Go | |
Eh | XBARCLR4 | X-Bar Input Flag Clear Register 4 | Go |
Complex bit access types are encoded to fit into small table cells. Table 11-32 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
R-0 | R -0 | Read Returns 0s |
Write Type | ||
W1S | W 1S | Write 1 to set |
Reset or Default Value | ||
-n | Value after reset or the default value | |
Register Array Variables | ||
i,j,k,l,m,n | When these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula. | |
y | When this variable is used in a register name, an offset, or an address it refers to the value of a register array. |
XBARFLG1 is shown in Figure 11-24 and described in Table 11-33.
Return to the Summary Table.
X-Bar Input Flag Register 1
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
CMPSS4_CTRIPOUTH | CMPSS4_CTRIPOUTL | CMPSS3_CTRIPOUTH | CMPSS3_CTRIPOUTL | CMPSS2_CTRIPOUTH | CMPSS2_CTRIPOUTL | CMPSS1_CTRIPOUTH | CMPSS1_CTRIPOUTL |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CMPSS4_CTRIPH | CMPSS4_CTRIPL | CMPSS3_CTRIPH | CMPSS3_CTRIPL | CMPSS2_CTRIPH | CMPSS2_CTRIPL | CMPSS1_CTRIPH | CMPSS1_CTRIPL |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RESERVED | R | 0h | Reserved |
30 | RESERVED | R | 0h | Reserved |
29 | RESERVED | R | 0h | Reserved |
28 | RESERVED | R | 0h | Reserved |
27 | RESERVED | R | 0h | Reserved |
26 | RESERVED | R | 0h | Reserved |
25 | RESERVED | R | 0h | Reserved |
24 | RESERVED | R | 0h | Reserved |
23 | CMPSS4_CTRIPOUTH | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: Corresponding Input was triggered 0: Corresponding Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
22 | CMPSS4_CTRIPOUTL | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: Corresponding Input was triggered 0: Corresponding Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
21 | CMPSS3_CTRIPOUTH | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: Corresponding Input was triggered 0: Corresponding Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
20 | CMPSS3_CTRIPOUTL | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: Corresponding Input was triggered 0: Corresponding Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
19 | CMPSS2_CTRIPOUTH | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: Corresponding Input was triggered 0: Corresponding Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
18 | CMPSS2_CTRIPOUTL | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: Corresponding Input was triggered 0: Corresponding Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
17 | CMPSS1_CTRIPOUTH | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: Corresponding Input was triggered 0: Corresponding Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
16 | CMPSS1_CTRIPOUTL | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: Corresponding Input was triggered 0: Corresponding Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
15 | RESERVED | R | 0h | Reserved |
14 | RESERVED | R | 0h | Reserved |
13 | RESERVED | R | 0h | Reserved |
12 | RESERVED | R | 0h | Reserved |
11 | RESERVED | R | 0h | Reserved |
10 | RESERVED | R | 0h | Reserved |
9 | RESERVED | R | 0h | Reserved |
8 | RESERVED | R | 0h | Reserved |
7 | CMPSS4_CTRIPH | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: Corresponding Input was triggered 0: Corresponding Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
6 | CMPSS4_CTRIPL | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: Corresponding Input was triggered 0: Corresponding Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
5 | CMPSS3_CTRIPH | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: Corresponding Input was triggered 0: Corresponding Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
4 | CMPSS3_CTRIPL | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: Corresponding Input was triggered 0: Corresponding Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
3 | CMPSS2_CTRIPH | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: Corresponding Input was triggered 0: Corresponding Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
2 | CMPSS2_CTRIPL | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: Corresponding Input was triggered 0: Corresponding Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
1 | CMPSS1_CTRIPH | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: Corresponding Input was triggered 0: Corresponding Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
0 | CMPSS1_CTRIPL | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: Corresponding Input was triggered 0: Corresponding Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
XBARFLG2 is shown in Figure 11-25 and described in Table 11-34.
Return to the Summary Table.
X-Bar Input Flag Register 2
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
ADCCEVT1 | ADCBEVT4 | ADCBEVT3 | ADCBEVT2 | ADCBEVT1 | ADCAEVT4 | ADCAEVT3 | ADCAEVT2 |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
ADCAEVT1 | EXTSYNCOUT | RESERVED | RESERVED | RESERVED | RESERVED | ECAP2_OUT | ECAP1_OUT |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
INPUT14 | INPUT13 | INPUT12 | INPUT11 | INPUT10 | INPUT9 | INPUT8 | INPUT7 |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ADCSOCB | ADCSOCA | INPUT6 | INPUT5 | INPUT4 | INPUT3 | INPUT2 | INPUT1 |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | ADCCEVT1 | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: Corresponding Input was triggered 0: Corresponding Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
30 | ADCBEVT4 | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: Corresponding Input was triggered 0: Corresponding Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
29 | ADCBEVT3 | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: Corresponding Input was triggered 0: Corresponding Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
28 | ADCBEVT2 | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: Corresponding Input was triggered 0: Corresponding Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
27 | ADCBEVT1 | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: Corresponding Input was triggered 0: Corresponding Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
26 | ADCAEVT4 | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: Corresponding Input was triggered 0: Corresponding Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
25 | ADCAEVT3 | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: Corresponding Input was triggered 0: Corresponding Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
24 | ADCAEVT2 | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: Corresponding Input was triggered 0: Corresponding Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
23 | ADCAEVT1 | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: Corresponding Input was triggered 0: Corresponding Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
22 | EXTSYNCOUT | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: Corresponding Input was triggered 0: Corresponding Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
21 | RESERVED | R | 0h | Reserved |
20 | RESERVED | R | 0h | Reserved |
19 | RESERVED | R | 0h | Reserved |
18 | RESERVED | R | 0h | Reserved |
17 | ECAP2_OUT | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: Corresponding Input was triggered 0: Corresponding Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
16 | ECAP1_OUT | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: Corresponding Input was triggered 0: Corresponding Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
15 | INPUT14 | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: Corresponding Input was triggered 0: Corresponding Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
14 | INPUT13 | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: Corresponding Input was triggered 0: Corresponding Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
13 | INPUT12 | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: Corresponding Input was triggered 0: Corresponding Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
12 | INPUT11 | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: Corresponding Input was triggered 0: Corresponding Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
11 | INPUT10 | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: Corresponding Input was triggered 0: Corresponding Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
10 | INPUT9 | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: Corresponding Input was triggered 0: Corresponding Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
9 | INPUT8 | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: Corresponding Input was triggered 0: Corresponding Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
8 | INPUT7 | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: Corresponding Input was triggered 0: Corresponding Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
7 | ADCSOCB | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: Corresponding Input was triggered 0: Corresponding Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
6 | ADCSOCA | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: Corresponding Input was triggered 0: Corresponding Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
5 | INPUT6 | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: Corresponding Input was triggered 0: Corresponding Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
4 | INPUT5 | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: Corresponding Input was triggered 0: Corresponding Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
3 | INPUT4 | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: Corresponding Input was triggered 0: Corresponding Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
2 | INPUT3 | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: Corresponding Input was triggered 0: Corresponding Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
1 | INPUT2 | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: Corresponding Input was triggered 0: Corresponding Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
0 | INPUT1 | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: Corresponding Input was triggered 0: Corresponding Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
XBARFLG3 is shown in Figure 11-26 and described in Table 11-35.
Return to the Summary Table.
X-Bar Input Flag Register 3
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | ADCEEVT4 | ADCEEVT3 | ADCEEVT2 |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
ADCEEVT1 | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ADCDEVT4 | ADCDEVT3 | ADCDEVT2 | ADCDEVT1 | ADCCEVT4 | ADCCEVT3 | ADCCEVT2 |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RESERVED | R | 0h | Reserved |
30 | RESERVED | R | 0h | Reserved |
29 | RESERVED | R | 0h | Reserved |
28 | RESERVED | R | 0h | Reserved |
27 | RESERVED | R | 0h | Reserved |
26 | RESERVED | R | 0h | Reserved |
25 | RESERVED | R | 0h | Reserved |
24 | RESERVED | R | 0h | Reserved |
23 | RESERVED | R | 0h | Reserved |
22 | RESERVED | R | 0h | Reserved |
21 | RESERVED | R | 0h | Reserved |
20 | RESERVED | R | 0h | Reserved |
19 | RESERVED | R | 0h | Reserved |
18 | ADCEEVT4 | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: Corresponding Input was triggered 0: Corresponding Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
17 | ADCEEVT3 | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: Corresponding Input was triggered 0: Corresponding Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
16 | ADCEEVT2 | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: Corresponding Input was triggered 0: Corresponding Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
15 | ADCEEVT1 | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: Corresponding Input was triggered 0: Corresponding Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
14 | RESERVED | R | 0h | Reserved |
13 | RESERVED | R | 0h | Reserved |
12 | RESERVED | R | 0h | Reserved |
11 | RESERVED | R | 0h | Reserved |
10 | RESERVED | R | 0h | Reserved |
9 | RESERVED | R | 0h | Reserved |
8 | RESERVED | R | 0h | Reserved |
7 | RESERVED | R | 0h | Reserved |
6 | ADCDEVT4 | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: Corresponding Input was triggered 0: Corresponding Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
5 | ADCDEVT3 | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: Corresponding Input was triggered 0: Corresponding Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
4 | ADCDEVT2 | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: Corresponding Input was triggered 0: Corresponding Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
3 | ADCDEVT1 | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: Corresponding Input was triggered 0: Corresponding Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
2 | ADCCEVT4 | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: Corresponding Input was triggered 0: Corresponding Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
1 | ADCCEVT3 | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: Corresponding Input was triggered 0: Corresponding Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
0 | ADCCEVT2 | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: Corresponding Input was triggered 0: Corresponding Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
XBARFLG4 is shown in Figure 11-27 and described in Table 11-36.
Return to the Summary Table.
X-Bar Input Flag Register 4
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
CLAHALT | RESERVED | RESERVED | ERRORSTS_ERROR | RESERVED | RESERVED | RESERVED | RESERVED |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RESERVED | RESERVED | RESERVED | CLB2_OUT5 | CLB2_OUT4 | CLB1_OUT5 | CLB1_OUT4 |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | MCANB_FEVT2 | MCANB_FEVT1 | MCANB_FEVT0 | MCANA_FEVT2 | MCANA_FEVT1 | MCANA_FEVT0 | RESERVED |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | CLAHALT | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: Corresponding Input was triggered 0: Corresponding Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
30 | RESERVED | R | 0h | Reserved |
29 | RESERVED | R | 0h | Reserved |
28 | ERRORSTS_ERROR | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: ERRORSTS_ERROR input was triggered 0: ERRORSTS_ERROR Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
27 | RESERVED | R | 0h | Reserved |
26 | RESERVED | R | 0h | Reserved |
25 | RESERVED | R | 0h | Reserved |
24 | RESERVED | R | 0h | Reserved |
23 | RESERVED | R | 0h | Reserved |
22 | RESERVED | R | 0h | Reserved |
21 | RESERVED | R | 0h | Reserved |
20 | RESERVED | R | 0h | Reserved |
19 | CLB2_OUT5 | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: Corresponding Input was triggered 0: Corresponding Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
18 | CLB2_OUT4 | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: Corresponding Input was triggered 0: Corresponding Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
17 | CLB1_OUT5 | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: Corresponding Input was triggered 0: Corresponding Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
16 | CLB1_OUT4 | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: Corresponding Input was triggered 0: Corresponding Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
15 | RESERVED | R | 0h | Reserved |
14 | MCANB_FEVT2 | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: MCANB_FEVT2 input was triggered 0: MCANB_FEVT2 Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
13 | MCANB_FEVT1 | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: MCANB_FEVT1 input was triggered 0: MCANB_FEVT1 Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
12 | MCANB_FEVT0 | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: MCANB_FEVT0 input was triggered 0: MCANB_FEVT0 Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
11 | MCANA_FEVT2 | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: MCANA_FEVT2 input was triggered 0: MCANA_FEVT2 Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
10 | MCANA_FEVT1 | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: MCANA_FEVT1 input was triggered 0: MCANA_FEVT1 Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
9 | MCANA_FEVT0 | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: MCANA_FEVT0 input was triggered 0: MCANA_FEVT0 Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
8 | RESERVED | R | 0h | Reserved |
7 | RESERVED | R | 0h | Reserved |
6 | RESERVED | R | 0h | Reserved |
5 | RESERVED | R | 0h | Reserved |
4 | RESERVED | R | 0h | Reserved |
3 | RESERVED | R | 0h | Reserved |
2 | RESERVED | R | 0h | Reserved |
1 | RESERVED | R | 0h | Reserved |
0 | RESERVED | R | 0h | Reserved |
XBARCLR1 is shown in Figure 11-28 and described in Table 11-37.
Return to the Summary Table.
X-Bar Input Flag Clear Register 1
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED |
R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
CMPSS4_CTRIPOUTH | CMPSS4_CTRIPOUTL | CMPSS3_CTRIPOUTH | CMPSS3_CTRIPOUTL | CMPSS2_CTRIPOUTH | CMPSS2_CTRIPOUTL | CMPSS1_CTRIPOUTH | CMPSS1_CTRIPOUTL |
R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED |
R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CMPSS4_CTRIPH | CMPSS4_CTRIPL | CMPSS3_CTRIPH | CMPSS3_CTRIPL | CMPSS2_CTRIPH | CMPSS2_CTRIPL | CMPSS1_CTRIPH | CMPSS1_CTRIPL |
R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RESERVED | R-0/W1S | 0h | Reserved |
30 | RESERVED | R-0/W1S | 0h | Reserved |
29 | RESERVED | R-0/W1S | 0h | Reserved |
28 | RESERVED | R-0/W1S | 0h | Reserved |
27 | RESERVED | R-0/W1S | 0h | Reserved |
26 | RESERVED | R-0/W1S | 0h | Reserved |
25 | RESERVED | R-0/W1S | 0h | Reserved |
24 | RESERVED | R-0/W1S | 0h | Reserved |
23 | CMPSS4_CTRIPOUTH | R-0/W1S | 0h | Writing 1 to a bit in this register clears the corresponding bit in the XBARFLG1 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
22 | CMPSS4_CTRIPOUTL | R-0/W1S | 0h | Writing 1 to a bit in this register clears the corresponding bit in the XBARFLG1 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
21 | CMPSS3_CTRIPOUTH | R-0/W1S | 0h | Writing 1 to a bit in this register clears the corresponding bit in the XBARFLG1 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
20 | CMPSS3_CTRIPOUTL | R-0/W1S | 0h | Writing 1 to a bit in this register clears the corresponding bit in the XBARFLG1 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
19 | CMPSS2_CTRIPOUTH | R-0/W1S | 0h | Writing 1 to a bit in this register clears the corresponding bit in the XBARFLG1 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
18 | CMPSS2_CTRIPOUTL | R-0/W1S | 0h | Writing 1 to a bit in this register clears the corresponding bit in the XBARFLG1 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
17 | CMPSS1_CTRIPOUTH | R-0/W1S | 0h | Writing 1 to a bit in this register clears the corresponding bit in the XBARFLG1 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
16 | CMPSS1_CTRIPOUTL | R-0/W1S | 0h | Writing 1 to a bit in this register clears the corresponding bit in the XBARFLG1 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
15 | RESERVED | R-0/W1S | 0h | Reserved |
14 | RESERVED | R-0/W1S | 0h | Reserved |
13 | RESERVED | R-0/W1S | 0h | Reserved |
12 | RESERVED | R-0/W1S | 0h | Reserved |
11 | RESERVED | R-0/W1S | 0h | Reserved |
10 | RESERVED | R-0/W1S | 0h | Reserved |
9 | RESERVED | R-0/W1S | 0h | Reserved |
8 | RESERVED | R-0/W1S | 0h | Reserved |
7 | CMPSS4_CTRIPH | R-0/W1S | 0h | Writing 1 to a bit in this register clears the corresponding bit in the XBARFLG1 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
6 | CMPSS4_CTRIPL | R-0/W1S | 0h | Writing 1 to a bit in this register clears the corresponding bit in the XBARFLG1 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
5 | CMPSS3_CTRIPH | R-0/W1S | 0h | Writing 1 to a bit in this register clears the corresponding bit in the XBARFLG1 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
4 | CMPSS3_CTRIPL | R-0/W1S | 0h | Writing 1 to a bit in this register clears the corresponding bit in the XBARFLG1 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
3 | CMPSS2_CTRIPH | R-0/W1S | 0h | Writing 1 to a bit in this register clears the corresponding bit in the XBARFLG1 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
2 | CMPSS2_CTRIPL | R-0/W1S | 0h | Writing 1 to a bit in this register clears the corresponding bit in the XBARFLG1 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
1 | CMPSS1_CTRIPH | R-0/W1S | 0h | Writing 1 to a bit in this register clears the corresponding bit in the XBARFLG1 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
0 | CMPSS1_CTRIPL | R-0/W1S | 0h | Writing 1 to a bit in this register clears the corresponding bit in the XBARFLG1 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
XBARCLR2 is shown in Figure 11-29 and described in Table 11-38.
Return to the Summary Table.
X-Bar Input Flag Clear Register 2
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
ADCCEVT1 | RESERVED | RESERVED | RESERVED | RESERVED | ADCAEVT4 | ADCAEVT3 | ADCAEVT2 |
R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
ADCAEVT1 | EXTSYNCOUT | RESERVED | RESERVED | RESERVED | RESERVED | ECAP2_OUT | ECAP1_OUT |
R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
INPUT14 | INPUT13 | INPUT12 | INPUT11 | INPUT10 | INPUT9 | INPUT8 | INPUT7 |
R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ADCSOCB | ADCSOCA | INPUT6 | INPUT5 | INPUT4 | INPUT3 | INPUT2 | INPUT1 |
R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | ADCCEVT1 | R-0/W1S | 0h | Writing 1 to a bit in this register clears the corresponding bit in the XBARILAT2 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
30 | RESERVED | R-0/W1S | 0h | Reserved |
29 | RESERVED | R-0/W1S | 0h | Reserved |
28 | RESERVED | R-0/W1S | 0h | Reserved |
27 | RESERVED | R-0/W1S | 0h | Reserved |
26 | ADCAEVT4 | R-0/W1S | 0h | Writing 1 to a bit in this register clears the corresponding bit in the XBARILAT2 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
25 | ADCAEVT3 | R-0/W1S | 0h | Writing 1 to a bit in this register clears the corresponding bit in the XBARILAT2 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
24 | ADCAEVT2 | R-0/W1S | 0h | Writing 1 to a bit in this register clears the corresponding bit in the XBARILAT2 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
23 | ADCAEVT1 | R-0/W1S | 0h | Writing 1 to a bit in this register clears the corresponding bit in the XBARILAT2 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
22 | EXTSYNCOUT | R-0/W1S | 0h | Writing 1 to a bit in this register clears the corresponding bit in the XBARILAT2 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
21 | RESERVED | R-0/W1S | 0h | Reserved |
20 | RESERVED | R-0/W1S | 0h | Reserved |
19 | RESERVED | R-0/W1S | 0h | Reserved |
18 | RESERVED | R-0/W1S | 0h | Reserved |
17 | ECAP2_OUT | R-0/W1S | 0h | Writing 1 to a bit in this register clears the corresponding bit in the XBARILAT2 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
16 | ECAP1_OUT | R-0/W1S | 0h | Writing 1 to a bit in this register clears the corresponding bit in the XBARILAT2 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
15 | INPUT14 | R-0/W1S | 0h | Writing 1 to a bit in this register clears the corresponding bit in the XBARILAT2 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
14 | INPUT13 | R-0/W1S | 0h | Writing 1 to a bit in this register clears the corresponding bit in the XBARILAT2 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
13 | INPUT12 | R-0/W1S | 0h | Writing 1 to a bit in this register clears the corresponding bit in the XBARILAT2 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
12 | INPUT11 | R-0/W1S | 0h | Writing 1 to a bit in this register clears the corresponding bit in the XBARILAT2 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
11 | INPUT10 | R-0/W1S | 0h | Writing 1 to a bit in this register clears the corresponding bit in the XBARILAT2 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
10 | INPUT9 | R-0/W1S | 0h | Writing 1 to a bit in this register clears the corresponding bit in the XBARILAT2 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
9 | INPUT8 | R-0/W1S | 0h | Writing 1 to a bit in this register clears the corresponding bit in the XBARILAT2 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
8 | INPUT7 | R-0/W1S | 0h | Writing 1 to a bit in this register clears the corresponding bit in the XBARILAT2 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
7 | ADCSOCB | R-0/W1S | 0h | Writing 1 to a bit in this register clears the corresponding bit in the XBARILAT2 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
6 | ADCSOCA | R-0/W1S | 0h | Writing 1 to a bit in this register clears the corresponding bit in the XBARILAT2 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
5 | INPUT6 | R-0/W1S | 0h | Writing 1 to a bit in this register clears the corresponding bit in the XBARILAT2 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
4 | INPUT5 | R-0/W1S | 0h | Writing 1 to a bit in this register clears the corresponding bit in the XBARILAT2 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
3 | INPUT4 | R-0/W1S | 0h | Writing 1 to a bit in this register clears the corresponding bit in the XBARILAT2 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
2 | INPUT3 | R-0/W1S | 0h | Writing 1 to a bit in this register clears the corresponding bit in the XBARILAT2 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
1 | INPUT2 | R-0/W1S | 0h | Writing 1 to a bit in this register clears the corresponding bit in the XBARILAT2 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
0 | INPUT1 | R-0/W1S | 0h | Writing 1 to a bit in this register clears the corresponding bit in the XBARILAT2 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
XBARCLR3 is shown in Figure 11-30 and described in Table 11-39.
Return to the Summary Table.
X-Bar Input Flag Clear Register 3
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED |
R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | ADCEEVT4 | ADCEEVT3 | ADCEEVT2 |
R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
ADCEEVT1 | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED |
R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ADCDEVT4 | ADCDEVT3 | ADCDEVT2 | ADCDEVT1 | ADCCEVT4 | ADCCEVT3 | ADCCEVT2 |
R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RESERVED | R-0/W1S | 0h | Reserved |
30 | RESERVED | R-0/W1S | 0h | Reserved |
29 | RESERVED | R-0/W1S | 0h | Reserved |
28 | RESERVED | R-0/W1S | 0h | Reserved |
27 | RESERVED | R-0/W1S | 0h | Reserved |
26 | RESERVED | R-0/W1S | 0h | Reserved |
25 | RESERVED | R-0/W1S | 0h | Reserved |
24 | RESERVED | R-0/W1S | 0h | Reserved |
23 | RESERVED | R-0/W1S | 0h | Reserved |
22 | RESERVED | R-0/W1S | 0h | Reserved |
21 | RESERVED | R-0/W1S | 0h | Reserved |
20 | RESERVED | R-0/W1S | 0h | Reserved |
19 | RESERVED | R-0/W1S | 0h | Reserved |
18 | ADCEEVT4 | R-0/W1S | 0h | Writing 1 to a bit in this register clears the corresponding bit in the XBARILAT3 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
17 | ADCEEVT3 | R-0/W1S | 0h | Writing 1 to a bit in this register clears the corresponding bit in the XBARILAT3 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
16 | ADCEEVT2 | R-0/W1S | 0h | Writing 1 to a bit in this register clears the corresponding bit in the XBARILAT3 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
15 | ADCEEVT1 | R-0/W1S | 0h | Writing 1 to a bit in this register clears the corresponding bit in the XBARILAT3 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
14 | RESERVED | R-0/W1S | 0h | Reserved |
13 | RESERVED | R-0/W1S | 0h | Reserved |
12 | RESERVED | R-0/W1S | 0h | Reserved |
11 | RESERVED | R-0/W1S | 0h | Reserved |
10 | RESERVED | R-0/W1S | 0h | Reserved |
9 | RESERVED | R-0/W1S | 0h | Reserved |
8 | RESERVED | R-0/W1S | 0h | Reserved |
7 | RESERVED | R-0/W1S | 0h | Reserved |
6 | ADCDEVT4 | R-0/W1S | 0h | Writing 1 to a bit in this register clears the corresponding bit in the XBARILAT3 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
5 | ADCDEVT3 | R-0/W1S | 0h | Writing 1 to a bit in this register clears the corresponding bit in the XBARILAT3 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
4 | ADCDEVT2 | R-0/W1S | 0h | Writing 1 to a bit in this register clears the corresponding bit in the XBARILAT3 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
3 | ADCDEVT1 | R-0/W1S | 0h | Writing 1 to a bit in this register clears the corresponding bit in the XBARILAT3 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
2 | ADCCEVT4 | R-0/W1S | 0h | Writing 1 to a bit in this register clears the corresponding bit in the XBARILAT3 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
1 | ADCCEVT3 | R-0/W1S | 0h | Writing 1 to a bit in this register clears the corresponding bit in the XBARILAT3 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
0 | ADCCEVT2 | R-0/W1S | 0h | Writing 1 to a bit in this register clears the corresponding bit in the XBARILAT3 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
XBARCLR4 is shown in Figure 11-31 and described in Table 11-40.
Return to the Summary Table.
X-Bar Input Flag Clear Register 4
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
CLAHALT | RESERVED | RESERVED | ERRORSTS_ERROR | RESERVED | RESERVED | RESERVED | RESERVED |
R-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RESERVED | RESERVED | RESERVED | CLB2_OUT5 | CLB2_OUT4 | CLB1_OUT5 | CLB1_OUT4 |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | MCANB_FEVT2 | MCANB_FEVT1 | MCANB_FEVT0 | MCANA_FEVT2 | MCANA_FEVT1 | MCANA_FEVT0 | RESERVED |
R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | CLAHALT | R | 0h | Writing 1 to a bit in this register clears the corresponding bit in the XBARILAT3 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
30 | RESERVED | R-0/W1S | 0h | Reserved |
29 | RESERVED | R-0/W1S | 0h | Reserved |
28 | ERRORSTS_ERROR | R-0/W1S | 0h | Writing 1 to this bit clears the ERRORSTS_ERROR bit in the XBARFLG4 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
27 | RESERVED | R-0/W1S | 0h | Reserved |
26 | RESERVED | R-0/W1S | 0h | Reserved |
25 | RESERVED | R-0/W1S | 0h | Reserved |
24 | RESERVED | R-0/W1S | 0h | Reserved |
23 | RESERVED | R | 0h | Reserved |
22 | RESERVED | R | 0h | Reserved |
21 | RESERVED | R | 0h | Reserved |
20 | RESERVED | R | 0h | Reserved |
19 | CLB2_OUT5 | R | 0h | Writing 1 to a bit in this register clears the corresponding bit in the XBARILAT3 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
18 | CLB2_OUT4 | R | 0h | Writing 1 to a bit in this register clears the corresponding bit in the XBARILAT3 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
17 | CLB1_OUT5 | R | 0h | Writing 1 to a bit in this register clears the corresponding bit in the XBARILAT3 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
16 | CLB1_OUT4 | R | 0h | Writing 1 to a bit in this register clears the corresponding bit in the XBARILAT3 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
15 | RESERVED | R-0/W1S | 0h | Reserved |
14 | MCANB_FEVT2 | R-0/W1S | 0h | Writing 1 to this bit clears the MCANB_FEVT2 bit in the XBARFLG4 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
13 | MCANB_FEVT1 | R-0/W1S | 0h | Writing 1 to this bit clears the MCANB_FEVT1 bit in the XBARFLG4 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
12 | MCANB_FEVT0 | R-0/W1S | 0h | Writing 1 to this bit clears the MCANB_FEVT0 bit in the XBARFLG4 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
11 | MCANA_FEVT2 | R-0/W1S | 0h | Writing 1 to this bit clears the MCANA_FEVT2 bit in the XBARFLG4 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
10 | MCANA_FEVT1 | R-0/W1S | 0h | Writing 1 to this bit clears the MCANA_FEVT1 bit in the XBARFLG4 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
9 | MCANA_FEVT0 | R-0/W1S | 0h | Writing 1 to this bit clears the MCANA_FEVT0 bit in the XBARFLG4 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
8 | RESERVED | R-0/W1S | 0h | Reserved |
7 | RESERVED | R | 0h | Reserved |
6 | RESERVED | R | 0h | Reserved |
5 | RESERVED | R | 0h | Reserved |
4 | RESERVED | R | 0h | Reserved |
3 | RESERVED | R | 0h | Reserved |
2 | RESERVED | R | 0h | Reserved |
1 | RESERVED | R | 0h | Reserved |
0 | RESERVED | R | 0h | Reserved |