SPRUJ53B April 2024 – September 2024 TMS320F28P550SJ , TMS320F28P559SJ-Q1
The memory-mapped CLB registers are described later in this chapter; however, many of the CLB resources including counters, the instruction memory of the High Level Controller, and the HLC general-purpose registers (R0 through R3) are only indirectly accessible through a local interface bus and are not memory-mapped. These registers are accessible through the two memory-mapped registers CLB_LOAD_DATA and CLB_LOAD_ADDR. Note that the general-purpose registers R0 through R3 must only be written to during configuration-time and are not intended to be written to during run-time. Writes during run-time can lead to unexpected behavior. If run-time data exchange is desired, refer to Section 30.4.7.4.
Load the data to be written into the CLB_LOAD_DATA register, then load the appropriate address into CLB_LOAD_ADDR to determine where this data is written. Writing a 1 to bit position 0 in the CLB_LOAD_EN register then causes an internal write operation to be triggered. The address allocation for the CLB_LOAD_ADDR register is shown in Table 30-15.
Address (Binary) | Resource |
---|---|
000000 to 000010 | Counter 0 to 2 Load value |
000100 to 000110 | Counter 0 to 2 Match1 value |
001000 to 001010 | Counter 0 to 2 Match2 value |
001100 to 001111 | R0 to R3 of High Level Controller |
100000 to 100111 | Instructions for Event 0 |
101000 to 101111 | Instructions for Event 1 |
110000 to 110111 | Instructions for Event 2 |
111000 to 111111 | Instructions for Event 3 |
Use the following steps to load the value 0x11223344 into the general purpose R0 register: