SPRUJ62 December   2022 AM69 , AM69A , TDA4AH-Q1 , TDA4AP-Q1 , TDA4VH-Q1 , TDA4VP-Q1

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 Inside the Box
    2. 1.2 Key Features and Interfaces
    3. 1.3 Thermal Compliance
    4. 1.4 Reach Compliance
    5. 1.5 EMC, EMI, and ESD Compliance
  3. 2User Interfaces
    1. 2.1 Power Input
      1. 2.1.1 Power Input [J7] [J3] with LED for Status [LD4][LD5]
      2. 2.1.2 Power Control [SW1] with LED for Status [LD7][LD8][LD9]
      3. 2.1.3 Power Budget Considerations
    2. 2.2 User Inputs
      1. 2.2.1 Board Configuration Settings [SW2] [SW4] [SW13] [SW16]
      2. 2.2.2 Boot Configuration Settings [SW7] [ SW11]
      3. 2.2.3 Reset Pushbuttons [SW9] [ SW10] [SW12] [SW14]
      4. 2.2.4 User Pushbuttons [SW3] [SW5] [SW6] [SW8] [SW15] with User LED Indication [LD2] [LD3]
    3. 2.3 Standard Interfaces
      1. 2.3.1 Uart-Over-USB [J48] [J49] with LED for Status [LD11] [LD12]
      2. 2.3.2 Gigabit Ethernet [J39] [J40] with Integrated LEDs for Status
      3. 2.3.3 USB3.1 Gen1 Interface [J4]
      4. 2.3.4 USB2.0 Interface [J5]
      5. 2.3.5 PCIe Card Slot [J14] [J17]
      6. 2.3.6 Display Port Interfaces [J8] [J9]
      7. 2.3.7 MicroSD Card Cage [J53]
      8. 2.3.8 Stereo Audio Interface [J29]
      9. 2.3.9 JTAG/Emulation Interface [J23] [J1]
    4. 2.4 Expansion Interfaces
      1. 2.4.1  Heatsink [ACC1] with Fan Header [J24]
      2. 2.4.2  CAN-FD Connectors [J41-J46]
      3. 2.4.3  LIN Connectors [J28]
      4. 2.4.4  Serial Ethernet Expansion Interfaces [J52] [J51]
      5. 2.4.5  Camera Interfaces [J55] [J57]
      6. 2.4.6  Automation and Control Connector [J50]
      7. 2.4.7  ADC [J27]
      8. 2.4.8  SPI [J26]
      9. 2.4.9  CSI-TX [J10]
      10. 2.4.10 Accessory Power Connector [J47]
  4. 3Circuit Details
    1. 3.1 Top Level Diagram
    2. 3.2 Interface Mapping
    3. 3.3 I2C Address Mapping
    4. 3.4 GPIO Mapping
    5. 3.5 Power Monitoring
    6. 3.6 Shared Interfaces / Signal Muxing
    7. 3.7 Power Delivery Network (PDN)
    8. 3.8 Identification EEPROM

2.2.1 Board Configuration Settings [SW2] [SW4] [SW13] [SW16]

Dip switches [SW2] [SW4] [SW13] [SW16] are used to configure different options available on the EVM.

Table 2-4 Dip Switch [SW2] [SW13] EVM Configuration Settings

[SW2]

Position

Default Function Description
SW2.1 OFF Octal-SPI Memory Selection

MUX to select between non-volatile Octal-SPI memory connected to the MCU_OSPI0 interface:

‘0’ (OFF) = xSPI Memory is selected

‘1’ (ON) = Octal-NAND is selected
SW2.2 ON Debug/Trace Enable

MUX to select between Debug/Trace (connected via MIPI 60 emulation interface) and variety of ‘other’ EVM features (1):

‘0’ (OFF) = ‘Other’ EVM features are selected/enabled

‘1’ (ON) = Debug/Trace is enabled to MIPI-60 emulation interface
SW2.[4:3] OFF:OFF USB Type C Mode Selection

Set Mode for USB Type C interface (USB0):

'00' (OFF/OFF) = DFP (Downstream Facing Port)

‘01’ (OFF/ON) = DRP (Dual Role Port)

‘1X’ (ON, Don’t Care) = UFP (Upstream Facing Port)
SW2.5 OFF PCIe0 Mode Selection

Set Mode for PCIe0 (4-Lane)

‘0’ (OFF) = Root Complex

‘1’ (ON) = End Point
SW2.6 OFF PCIe1 Mode Selection

Set Mode for PCIe1 (2-Lane)

‘0’ (OFF) = Root Complex

‘1’ (ON) = End Point
SW2.7 ON IO Voltage for Serial Camera Add-on Board(s)

Configures IO supply for Serial Camera Expansion Interface (I2C, GPIO, etc). Voltage levels of CSI2-RX signals is defined by MIPI specification.

‘0’ (OFF) = IO Levels are set to 3.3VDC

‘1’ (ON) = IO Levels are set to 1.8VDC
SW2.8 ON Reserved

Reserved for future feature enhancement. Must be set to ‘1’ (ON) for EVM to function correctly.

‘0’ (OFF) = Invalid setting

‘1’ (ON) = Must be set to ‘1’
SW2.9 ON EVM Configuration EEPROM Write Protection

Sets EVM’s configuration EEPROM Write Protection

‘0’ (OFF) = Configuration EEPROM can be updated

‘1’ (ON) = Configuration EEPROM cannot be updated/is protected
SW2.10 ON User Defined

User Defined, maps to GPIO/IO Expander Input (See GPIO tables)

‘0’ (OFF) = User Defined

‘1’ (ON) = User Defined
SW13.1 OFF LIN1 Mode Selection

Configure Master/Slave mode for LIN1 Interface

‘0’ (OFF) = Slave Mode

‘1’ (ON) = Master Mode
SW13.2 OFF LIN2 Mode Selection

Configure Master/Slave mode for LIN2 Interface

‘0’ (OFF) = Slave Mode

‘1’ (ON) = Master Mode
Note: A variety of signals multiplex with the Debug/Trace interface on the processor. If Trace is enabled, the following signals are no longer available on the EVM (impacting some peripherals), including: Audio, CAN Bus 4/5, and RGMII1 Ethernet.

Table 2-5 shows the J7AHP EVM configuration switches [SW4] [SW16] to set the various Power Management IC (PMIC) and reset functions.

Table 2-5 Dip Switch [SW4][SW16] EVM Configuration Settings

[SW16]

Position

Default Function Description
SW4.1 OFF

Reserved / Test Mode

(Wait Reset)

 Reserved, Must set to ‘0’ (OFF) for normal EVM operation (only used in Test Mode)
SW4.2 OFF

Reserved / Test Mode

(Wait Reset)

 Reserved, Must set to ‘0’ (OFF) for normal EVM operation (only used in Test Mode)
SW16.1 ON Reserved / Tests Mode (PMIC Enable)

Reserved, Must set to ‘1’ (ON) for normal EVM operation (only used in Test Mode)

‘0’ (OFF) = Disable PMIC (Do Not Use)

‘1’ (ON) = Enable PMIC
SW16.2 ON Reserved / Test Mode (VMonitor Enable)

Reserved, Must set to ‘1’ (ON) for normal EVM operation (only used in Test Mode)

‘0’ (OFF) = Disable Voltage Monitor (Do Not Use)

‘1’ (ON) = Enable Voltage Monitor
SW16.3 ON

Reserved / Test Mode

(Disable)

Reserved, Must set to ‘1’ (ON) for normal EVM operation

‘0’ (OFF) = Enable Test Mode (Do Not Use)

‘1’ (ON) = Disable Test Mode
SW16.4 ON Watchdog Disable

Enable/Disable of Watchdog Timer within PMIC. (Note this can cause processor reset if watchdog is not managed.)

‘0’ (OFF) = Watchdog Timer is Enabled

‘1’ (ON) = Watchdog Timer is Disabled