SPRUJ74 January   2023

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 Key Features
    2. 1.2 Thermal Compliance
    3. 1.3 EMC, EMI, and ESD Compliance
  3. 2QP-ENET Board Identification and Installation
    1. 2.1 QP-ENET Board Component Identification
    2. 2.2 Interfacing QP-ENET Expansion Board with J784S4XG01EVM Board
      1. 2.2.1 Detailed Board Assembly Procedure (J784S4XG01EVM)
  4. 3QP-ENET Expansion Board Hardware Architecture
    1. 3.1 QP-ENET Expansion Board Hardware Top Level Diagram
    2. 3.2 Expansion Connectors
    3. 3.3 Board ID EEPROM
    4. 3.4 Ethernet Interface
      1. 3.4.1 Quad Port SGMII PHY Default Configuration
      2. 3.4.2 SGMII Clocking Scheme
        1. 3.4.2.1 Main Clock
        2. 3.4.2.2 Optional Clock
      3. 3.4.3 Ethernet Port LED Indication
      4. 3.4.4 Reset and Power-down Signals
  5. 4Revision History
  6.   A Appendix
    1.     A.1 Appendix – I (Interface Mapping)
    2.     A.2 Appendix – II (QP-ENET Board GPIO Mapping)

3.4.2.2 Optional Clock

Optionally, the reference clock can be supplied by the SERDES clock generator Mfr. Part Number# CDCI6214RGET located on QP-ENET Board, which can be configured by I2C0 of the J7 SOC. The I2C address of this clock generator is 0x77, and this address conflicts with the CDCI Chip on EVM Boards. An I2C switch on the Quad port Ethernet Expansion Board is used to remove the address conflict by connecting any one of the clock generators.

GUID-F206C285-12D3-461F-A70B-6BDE674ABE20-low.png Figure 3-4 Clock Source I2C MUX
GUID-764F0294-776D-401A-A464-539CDCAC7757-low.png Figure 3-5 QP-ENET Optional Clock Source

Setting the CDCI_I2C_SEL IO EXP bit high will connect the I2C bus to CDCI (for programming) on the Quad Port Ethernet Expansion Board. During this time, the CDCI device on the EVM boards should be in reset mode. Also, there are resistor options provided that must be adjusted to reflect any change in source clock selection; this is given in the following images.

GUID-A63B5219-627A-41A0-A27A-27828E91F50C-low.png Figure 3-6 SGMII PHY Clock Input Source Path Selection
GUID-6F17E6B8-6310-4E9A-A8FB-A254C8B73785-low.png Figure 3-7 SGMII PHY Clock Configuration