SPRUJ81A February   2023  – January 2025 AM62A1-Q1 , AM62A3 , AM62A3-Q1 , AM62A7 , AM62A7-Q1 , AM62D-Q1

 

  1.   1
  2.   Trademarks
  3. 1 Introduction
  4. 2 Width/Spacing Proposal for Escapes
  5. 3 Stackup
  6. 4 Via Sharing
  7. 5 Floorplan Component Placement
  8. 6 Critical Interfaces Impact Placement
  9. 7 Routing Priority
  10. 8 SerDes Interfaces
  11. 9 DDR Interfaces
  12. 10Power Decoupling
  13. 11Route Lowest Priority Interfaces Last
  14. 12Summary
  15. 13References
  16. 14Revision History

8 SerDes Interfaces

The package BGA ball map is also arranged to support routing the high priority interfaces first. Therefore, the SerDes CSI interfaces are located close to the outer rings. The lanes located on the outermost row of BGAs can be escaped on the top layer. The lanes located on inner BGA rows require vias to escape as a differential pair on the bottom or on an interior layer. The BGA map facilitates this for inner rows. Figure 8-1 shows an example of the SerDes signals on the AM62Ax/AM62Dx board on the top layer and on an inner layer. Wide traces can limit the signal loss but could violate the impedance requirements. For more detailed information on routing Serdes signals, see the High-Speed Interface Layout Guidelines.

Serdes CSI Escapes for Top Layer (Left) and Inner Layer (Right) Figure 8-1 Serdes CSI Escapes for Top Layer (Left) and Inner Layer (Right)