SPRUJ81 February 2023 AM62A3 , AM62A3-Q1 , AM62A7 , AM62A7-Q1
PCB stack-up is one of the first and most important considerations in realizing a successful PCB. The AM62Ax device supports a BGA array of 22x22 with a 0.8-mm pitch and a body size of 18 mm. Due to the number of rows of signal balls around the periphery, TI recommends three signal routing layers. PDN compliance and robustness is critical to meet all the performance objectives of the device and associated peripherals. To enable this, TI recommends allocating three layers for power planes. Ground planes must be added adjacent to the power planes and adjacent to the outer layers for shielding and controlled impedance routing. High speed interfaces such as DDR, CSI, and USB require ground planes for impedance matching. Additionally, to meet the higher DDR interface speeds, ground layers both above and below the DDR signals are recommended. The escapes and routing on the AM62Ax board design was achieved with 12 layers as shown in the following table.
PCB Layer | Layer Routing, Planes or Pours |
---|---|
Layer 1 | Component pads, ground, and signal escapes |
Layer 2 | Ground |
Layer 3 | Signal Routing |
Layer 4 | Ground |
Layer 5 | Signal Routing |
Layer 6 | Power/Ground ref for DDR |
Layer 7 | Power |
Layer 8 | Power |
Layer 9 | Ground |
Layer 10 | Signal Routing |
Layer 11 | Ground |
Layer 12 | Component pads, power, and ground routes |
An example 12-layer board stack-up for AM62Ax is described above. This board is designed for optimum signal integrity on the high-speed interfaces while limiting the board size. The AM62Ax board is implemented without HDI (High Density Interconnect) and does not use micro vias, which are both intended to save board cost. All vias on the AM62Ax board are Plated Through Hole (PTH) and pass completely through the board. Proper analysis shall be performed to validate both signal and power integrity, if further optimizations are required to reduce PCB stack-up and/or routing rules illustrated in this document.