SPRUJ85 April   2024

ADVANCE INFORMATION  

  1.   1
  2.   Description
  3.   Key Features
  4. 1LaunchPad Module Overview
    1. 2.1 Introduction
    2. 2.2 Preface: Read This First
      1. 2.2.1 If You Need Assistance
      2. 2.2.2 Important Usage Notes
    3. 2.3 Kit Contents
    4. 2.4 Device Information
      1. 2.4.1 System Architecture Overview
      2. 2.4.2 Security
      3. 2.4.3 Compliance
      4. 2.4.4 BoosterPacks
      5. 2.4.5 Component Identification
  5. 2Hardware Description
    1. 3.1  Board Setup
      1. 3.1.1 Power Requirements
        1. 3.1.1.1 Power Input Using USB Type-C Connector
        2. 3.1.1.2 Power Status LEDs
        3. 3.1.1.3 Power Tree
      2. 3.1.2 Push Buttons
      3. 3.1.3 Boot mode Selection
      4. 3.1.4 IO Expander
    2. 3.2  Functional Block Diagram
    3. 3.3  GPIO Mapping
    4. 3.4  Reset
    5. 3.5  Clock
    6. 3.6  Memory Interface
      1. 3.6.1 OSPI
      2. 3.6.2 Board ID EEPROM
    7. 3.7  Ethernet Interface
      1. 3.7.1 Ethernet PHY #1 - CPSW RGMII/ICSSM
      2. 3.7.2 Ethernet PHY #2 - CPSW RGMII/ICSSM
      3. 3.7.3 LED Indication in RJ45 Connector
    8. 3.8  I2C
    9. 3.9  Industrial Application LEDs
    10. 3.10 SPI
    11. 3.11 UART
    12. 3.12 MCAN
    13. 3.13 FSI
    14. 3.14 JTAG
    15. 3.15 TIVA and Test Automation Header
    16. 3.16 LIN
    17. 3.17 MMC
    18. 3.18 ADC and DAC
    19. 3.19 EQEP and SDFM
    20. 3.20 EPWM
    21. 3.21 BoosterPack Headers
    22. 3.22 Pinmux Mapping
  6. 3Additional Information
    1.     Trademarks
    2. 4.1 Sitara MCU+ Academy
  7. 4References
    1. 5.1 Reference Documents
    2. 5.2 Other TI Components Used in This Design
  8. 5Revision History

2.1.3 Boot mode Selection

The boot mode for the AM263Px is selected by a DIP (Dual In-Line Package) switch (SW1) or the test automation header. The test automation header uses an I2C expansion buffer to drive the boot mode when PORz is toggled. The supported boot modes are shown in Table 2-6. The DIP Switch configurations for each boot mode are shown in Table 2-5.


GUID-20240108-SS0I-WSW1-FZRS-QFSD62GDWGQM-low.png

Figure 2-6 Boot mode DIP Switch Positions - LP AM263Px E2 SW1 SOP Switches
Table 2-5 Boot mode Selection
Boot mode SPI0_D0_pad (SOP3 - SW1.4) SPI0_CLK_pad (SOP2 - SW1.3) QSPI_D1 (SOP1 - SW1.2) QSPI_D0 (SOP0 - SW1.1)
OSPI (4S) - Quad Read Mode 1 1 1 1
UART 1 1 1 0
OSPI (1S) - Single Read Mode 1 1 0 1
OSPI (8S) - Octal Read Mode 1 1 0 0
DevBoot 0 1 0 0
xSPI 8D (SFDP) 0 0 1 1
Unsupported boot mode All other combinations not defined above
Table 2-6 Supported Boot modes
Boot mode/Peripheral Boot Media/Host Notes
OSPI (4S) - Quad Read Mode OSPI Flash

Download and boot SBL from OSPI flash in quad read mode. Attempt Primary SBL, followed by Secondary SBL if primary loading fails.
UART External Host

Download and boot SBL from UART interface via XMODEM protocol at 115200bps BaudRate.
OSPI (1S) - Single Read Mode OSPI Flash

Download and boot SBL from OSPI flash in single read mode. Attempt Primary SBL, followed by Secondary SBL if primary loading fails.
OSPI (8S) - Octal Read Mode OSPI Flash

Download and boot SBL from OSPI flash in octal read mode. Attempt Primary SBL, followed by Secondary SBL if primary loading fails.
xSPI 8D (SFDP) OSPI Flash

Read SFDP table for read command, download and boot SBL from OSPI flash in 8D mode. Attempt Primary SBL, followed by Secondary SBL if primary loading fails.
DevBoot N/A No SBL. Used for development purposes only.