SPRUJ85A April   2024  – August 2024

PRODUCTION DATA  

  1.   1
  2.   Description
  3. 1Key Features
  4. 2LaunchPad Module Overview
    1. 3.1 Introduction
    2. 3.2 Preface: Read This First
      1. 3.2.1 If You Need Assistance
      2. 3.2.2 Important Usage Notes
    3. 3.3 Kit Contents
    4. 3.4 Device Information
      1. 3.4.1 System Architecture Overview
      2. 3.4.2 Security
      3. 3.4.3 Compliance
      4. 3.4.4 BoosterPacks
      5. 3.4.5 Component Identification
  5. 3Hardware Description
    1. 4.1  Board Setup
      1. 4.1.1 Power Requirements
        1. 4.1.1.1 Power Input Using USB Type-C Connector
        2. 4.1.1.2 Power Status LEDs
        3. 4.1.1.3 Power Tree
      2. 4.1.2 Push Buttons
      3. 4.1.3 Boot mode Selection
      4. 4.1.4 IO Expander
    2. 4.2  Functional Block Diagram
    3. 4.3  GPIO Mapping
    4. 4.4  Reset
    5. 4.5  Clock
    6. 4.6  Memory Interfaces
      1. 4.6.1 OSPI
      2. 4.6.2 MMC
      3. 4.6.3 eMMC
      4. 4.6.4 Board ID EEPROM
    7. 4.7  Ethernet Interface
      1. 4.7.1 Ethernet PHY #1 - CPSW RGMII/ICSSM
      2. 4.7.2 Ethernet PHY #2 - CPSW RGMII/ICSSM
      3. 4.7.3 LED Indication in RJ45 Connector
    8. 4.8  I2C
    9. 4.9  Industrial Application LEDs
    10. 4.10 SPI
    11. 4.11 UART
    12. 4.12 MCAN
    13. 4.13 FSI
    14. 4.14 JTAG
    15. 4.15 TIVA and Test Automation Header
    16. 4.16 LIN
    17. 4.17 ADC and DAC
    18. 4.18 EQEP and SDFM
    19. 4.19 EPWM
    20. 4.20 BoosterPack Headers
    21. 4.21 Pinmux Mapping
  6. 4Additional Information
    1.     Trademarks
    2. 5.1 Sitara MCU+ Academy
    3. 5.2 Known Board Changes/Issues
      1. 5.2.1 OSPI DQS and LBCLK nets swap
      2. 5.2.2 XDS110 Debugger Bricking Issue
      3. 5.2.3 eMMC CMD and CLK nets swap
  7. 5References
    1. 6.1 Reference Documents
    2. 6.2 Other TI Components Used in This Design
  8. 6Revision History

3.21 Pinmux Mapping

The various pinmux options for the BoosterPack connector pins are given below.

Table 3-24 Pinmux Legend
Default signal for BP Header Muxed alternative signal External MUX for alternate signal options
Table 3-25 Pinmux Options for J1
Pin# Mode0 Mode1 Mode2 Mode3 Mode4 Mode5 Mode6 Mode7 Mode8 Mode9 Mode 10
J1.1 3V3
J1.2 ADC0_AIN3
J1.3 EPWM15_B UART5_RXD MII1_CRS MCAN7_TX GPIO74 CHANNEL5 EPWM15_B
J1.4 EPWM15_A UART5_TXD MII1_COL MCAN7_RX GPIO73 CHANNEL4 EPWM15_A
J1.5 PR0_PRU0_GPIO12 RMII2_TXD1 RGMII2_TD1 MII2_TXD1 EPWM28_B GPIO100 EPWM28_B
J1.6 ADC1_AIN3
J1.7 SPI0_CLK UART3_TXD LIN3_TXD FSITX0_CLK GPIO12 CHANNEL1
PR0_PRU0_GPIO16 RGMII2_TXC MII2_TXCLK EPWM27_A GPIO97 EPWM27_A
J1.8 PR0_PRU0_GPIO10 RMII2_CRS_DV PR0_UART0_RTSn MII2_CRS EPWM23_A GPIO89 EPWM22_B
J1.9 EPWM8_B UART4_RXD I2C3_SCL SPI6_D1 FSITX2_D0 GPIO60 EPWM9_B
J1.10 EPWM8_A UART4_TXD I2C3_SDA SPI6_D0 FSITX2_CLK GPIO59 EPWM8_A
Table 3-26 Pinmux Options for J2
Pin# Mode0 Mode1 Mode2 Mode3 Mode4 Mode5 Mode6 Mode7 Mode8 Mode9 Mode10
J2.11 EPWM0_A GPIO43 EPWM0_A
J2.12 PR0_PRU0_GPIO15 RMII2_TX_EN RGMII2_TX_CTL MII2_TX_EN EPWM27_B GPIO98
J2.13 PR0_PRU0_GPIO5 RMII2_RX_ER MII2_RX_ER EPWM22_A GPIO87 EPWM22_A
J2.14 SPI1_D1 UART5_RXD XBAROUT4 FSIRX0_D1 GPIO18 CHANNEL7
PR0_PRU0_GPIO14 RGMII2_TD3 MII2_TXD3 EPWM29_B GPIO102 EPWM27_B
J2.15 SPI1_D0 UART5_TXD XBAROUT3 FSIRX0_D0 GPIO17 CHANNEL8
PR0_PRU0_GPIO13 RGMII2_TD2 MII2_TXD2 EPWM29_A GPIO101 EPWM27_B
J2.16 PORz
J2.17 PR0_PRU0_GPIO4 RGMII2_RX_CTL MII2_RXDV EPWM24_B GPIO92 EPWM24_B
J2.18 SPI0_CS0 UART3_RXD LIN3_RXD GPIO11 CHANNEL0
PR0_PRU0_GPIO8 EPWM23_B GPIO90 EPWM29_A
J2.19 PR0_PRU0_GPIO3 RGMII2_RD3 MII2_RXD3 EPWM26_B GPIO96 EPWM26_B
J2.20 GND
Table 3-27 Pinmux Options for J3
Pin# Mode0 Mode1 Mode2 Mode3 Mode4 Mode5 Mode6 Mode7 Mode8 Mode9
J3.21 5V
J3.22 GND
J3.23 ADC0_AIN0
J3.24 ADC1_AIN0
J3.25 ADC2_AIN0
J3.26 ADC3_AIN0
J3.27 ADC4_AIN0
J3.28 ADC0_AIN1
J3.29 ADC1_AIN1
J3.30 DAC_OUT1
Table 3-28 Pinmux Options for J4
Pin# Mode0 Mode1 Mode2 Mode3 Mode4 Mode5 Mode6 Mode7 Mode8 Mode9 Mode10
J4.31 PR0_PRU0_GPIO2 RGMII2_RD2 MII2_RXD2 EPWM26_A GPIO95 EPWM26_A
J4.32 PR0_PRU0_GPIO1 RMII2_RXD1 RGMII2_RD1 MII2_RXD1 EPWM25_B GPIO94 EPWM25_B
J4.33 PR0_PRU0_GPIO0 RMII2_RXD0 RGMII2_RD0 MII2_RXD0 EPWM25_A GPIO93 EPWM25_A
J4.34 EPWM15_A UART5_TXD MII1_COL MCAN7_RX GPIO73 CHANNEL4 EPWM15_A
J4.35 EPWM14_A UART1_DSRn SPI7_D1 MCAN6_RX GPIO71 EPWM14_A
J4.36 EPWM14_B MII1_RX_ER GPIO72 EPWM14_B
J4.37 EPWM1_A GPIO45 EPWM1_A
J4.38 EPWM1_B GPIO46 EPWM4_B
J4.39 EPWM2_A GPIO47 EPWM2_A
J4.40 EPWM2_B GPIO48 EPWM2_B
Table 3-29 Pinmux Options for J5
Pin# Mode0 Mode1 Mode2 Mode3 Mode4 Mode5 Mode6 Mode7 Mode8 Mode9 Mode10
J5.41 3V3
J5.42 ADC2_AIN3
J5.43 LIN2_RXD UART2_RXD SPI2_D0 GPIO21
PR0_PRU0_GPIO11 RMII2_TXD0 RGMII2_TD0 MII2_TXD0 EPWM28_A GPIO99 EPWM28_A
J5.44 LIN2_TXD UART2_TXD SPI2_D1 GPIO22
PR0_PRU0_GPIO9 PR0_UART0_CTSn MII2_COL EPWM22_B GPIO88
J5.45 EPWM15_B UART5_RXD MII1_CRS MCAN7_TX GPIO74 CHANNEL5 EPWM15_B
J5.46 ADC3_AIN3
J5.47 SPI1_CLK UART4_RXD LIN4_RXD XBAROUT2 FSIRX0_CLK GPIO16 CHANNEL5
J5.48 PR0_PRU0_GPIO6 RMII2_REF_CLK RGMII2_RXC MII2_RXCLK EPWM24_A GPIO91 EPWM24_A
J5.49 I2C1_SCL SPI3_CS0 XBAROUT7 GPIO23
J5.50 I2C1_SDA SPI3_CLK XBAROUT8 GPIO24
Table 3-30 Pinmux Options for J6
Pin# Mode0 Mode1 Mode2 Mode3 Mode4 Mode5 Mode6 Mode7 Mode8 Mode9 Mode10
J6.51 EPWM7_B SPI6_CLK GPIO58 EPWM5_B
J6.52 EPWM4_A GPIO51 EPWM4_A
J6.53 EPWM12_A UART3_CTSn SPI4_CS1 MCAN7_RX OSPI_D5 GPIO67 EPWM12_A
J6.54 SPI0_D1 FSITX0_D1 GPIO14 CHANNEL3
J6.55 SPI0_D0 FSITX0_D0 GPIO13 CHANNEL2
J6.56 PORz
J6.57 EPWM12_B UART1_DCDn SPI7_CS0 MCAN7_TX OSPI_D7 GPIO68 EPWM10_A
J6.58 SPI1_CS0 UART4_TXD LIN4_TXD XBAROUT1 GPIO15 CHANNEL4
J6.59 EPWM0_B GPIO44 EPWM0_B
J6.60 GND
Table 3-31 Pinmux Options for J7
Pin# Mode0 Mode1 Mode2 Mode3 Mode4 Mode5 Mode6 Mode7 Mode8 Mode9
J7.61 5V
J7.62 GND
J7.63 ADC2_AIN1
PR0_PRU1_GPIO16 MCAN5_RX FSITX3_CLK TRC_DATA10 GPIO113
J7.64 ADC3_AIN1
PR0_PRU1_GPIO15 MCAN5_TX FSITX3_D0 TRC_DATA11 GPIO114
J7.65 ADC4_AIN1
LIN1_RXD UART1_RXD SPI2_CS0 OSPI_ECC_FAIL XBAROUT5 GPIO19 OSPI_RESET_OUT1
J7.66 ADC0_AIN2
LIN1_TXD UART1_TXD SPI2_CLK OSPI_RESET_OUT0 XBAROUT6 GPIO20
J7.67 ADC1_AIN2
UART5_RXD GPIO127 SDFM0_D2 CHANNEL0
J7.68 ADC2_AIN2
UART5_TXD I2C3_SCL GPIO126 SDFM0_CLK2 CHANNEL8
J7.69 ADC3_AIN2
MCAN3_RX GPIO129 SDFM0_D3 CHANNEL1
J7.70 DAC_OUT
MCAN3_TX UART5_RXD GPIO128 SDFM0_CLK3 CHANNEL9
Table 3-32 Pinmux Options for J8
Pin# Mode0 Mode1 Mode2 Mode3 Mode4 Mode5 Mode6 Mode7 Mode8 Mode9 Mode10
J8.71 PR0_PRU1_GPIO18 UART3_TXD PR0_IEP0_EDIO_DATA_IN_OUT31 TRC_CTL XBAROUT14 GPIO120 EQEP1_B
J8.72 PR0_PRU1_GPIO19 UART3_RXD PR0_IEP0_EDC_SYNC_OUT0 TRC_CLK XBAROUT13 GPIO119 EQEP1_A
J8.73 PR0_PRU1_GPIO17 UART5_CTSn PR0_IEP0_EDIO_DATA_IN_OUT30 GPIO125 SDFM0_D1
J8.74 PR0_PRU1_GPIO7 CPTS0_TS_SYNC UART5_RTSn PR0_IEP0_EDC_SYNC_OUT1 I2C3_SDA GPIO124 SDFM0_CLK1
J8.75 EPWM9_A SPI7_CS0 MCAN4_RX FSITX2_DATA1 GPIO61 EPWM9_A
J8.76 EPWM9_B UART1_RTSn SPI7_CLK MCAN4_TX FSIRX2_CLK GPIO62 EPWM11_B
J8.77 EPWM3_A GPIO49 EPWM3_A
J8.78 EPWM3_B GPIO50 EPWM6_A
J8.79 EPWM13_A UART1_RIn SPI7_CLK OSPI_D3 GPIO69 EPWM13_A
J8.80 EPWM13_B UART1_DTRn SPI7_D0 OSPI_ECC_FAIL GPIO70 EPWM13_B
Table 3-33 Pinmux Legend
Default signal for BP Header Muxed alternative signal External MUX for alternate signal options