SPRUJ86C October   2023  – August 2024 AM263P4 , AM263P4-Q1

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1Evaluation Module Overview
    1. 1.1 Introduction
      1.      Preface: Read This First
        1. 1.1.1.1 Sitara MCU+ Academy
        2. 1.1.1.2 Important Usage Notes
    2. 1.2 Kit Contents
    3. 1.3 Device Information
      1. 1.3.1 HSEC 180-pin Control Card Docking Station
      2. 1.3.2 Security
  6. 2Hardware
    1. 2.1  Component Identification
    2. 2.2  Power Requirements
      1. 2.2.1 Power Input Using USB Type-C Connector
      2. 2.2.2 Power Status LEDs
      3. 2.2.3 Power Tree
      4. 2.2.4 Power Sequence
      5. 2.2.5 PMIC
    3. 2.3  Functional Block Diagram
    4. 2.4  Reset
    5. 2.5  Clock
    6. 2.6  Boot Mode Selection
    7. 2.7  JTAG Path Selection
    8. 2.8  Header Information
    9. 2.9  GPIO Mapping
    10. 2.10 Push Buttons
    11. 2.11 Interfaces
      1. 2.11.1  Memory Interface
        1. 2.11.1.1 OSPI/QSPI
        2. 2.11.1.2 Board ID EEPROM
      2. 2.11.2  Ethernet Interface
        1. 2.11.2.1 Control Card Ethernet Routing
        2. 2.11.2.2 On Board Ethernet PHY
        3. 2.11.2.3 LED Indication in RJ45 Connector
        4. 2.11.2.4 Ethernet Add On Board Connector
      3. 2.11.3  I2C
      4. 2.11.4  Industrial Application LEDs
      5. 2.11.5  SPI
      6. 2.11.6  UART
      7. 2.11.7  MCAN
      8. 2.11.8  FSI
      9. 2.11.9  JTAG
      10. 2.11.10 Test Automation Header
      11. 2.11.11 LIN
      12. 2.11.12 MMC
      13. 2.11.13 ADC and DAC
    12. 2.12 HSEC Pinout and Pinmux Mapping
  7. 3Hardware Design Files
  8. 4Additional Information
    1. 4.1 If You Need Assistance
    2. 4.2 Trademarks
  9. 5Related Documentation
    1. 5.1 Supplemental Content
      1.      5.1.A E1 Board Modifications
      2.      5.1.B E2 Design Changes
      3.      5.1.C A Design Changes
  10. 6References
    1. 6.1 Reference Documents
    2. 6.2 Other TI Components Used in This Design
  11. 7Revision History
  12. 8Revision History

2.11.2.1 Control Card Ethernet Routing

The AM263Px SoC includes multiple Ethernet Ports and MDIO modules that can be routed to different locations based upon MUX/analog switch settings as well as which 0Ω resistors are populated on the board. There are three single-pole single-throw (SPST) switches as well as IO control signals from the IO expander that determine the state of the MUX/analog switch routing.

Figure 2-20 Shows a high-level overview of the routing scheme for all ethernet ports and MDIO signals.

Table 2-16 details the various available configurations for ethernet and MDIO routing on the Control Card. The Default setting is configuration 1 which is also highlighted in green.

Note: Various configurations require soldering and removal of 0Ω resistors.

AM263P1, AM263P1-Q1, AM263P2, AM263P2-Q1, AM263P4, AM263P4-Q1 Ethernet Routing Overview Figure 2-20 Ethernet Routing Overview
Represents the default state out-of-box Represents areas that require soldering/desoldering components
Table 2-16 Ethernet Routing
SoC Source Destination Config. # ICSSM0_
MUX_SEL (SW14)		 ICSSM1_
MUX_SEL (SW16)		 ICSSM2_
MUX_SEL (SW15)		 MDIO/MDC_
MUX_SEL1		 MDIO/MDC_
MUX_SEL2		 R476:R484 R493:R500 R509:R516 R525:R532 R485:R492 R501:R508 R517:R524 R533:R540
Controlled by IO expander OR SW[14:16] Controlled by IO expander Requires soldering and removing components
CPSW RGMII2 On-board PHY 1 Default Low Low Low High Low POP POP DNI DNI
PRU1 MII1 Ethernet Add-on Connector
N/A HSEC
PRU MII0 Not Connected
PRU0 MII0 On-board PHY 2 Low Low Low Low Low POP POP DNI DNI
PRU1 MII1 Ethernet Add-on Connector
N/A HSEC
CPSW RGMII2 Not Connected
PRU1 MII1 On-board PHY 3 Low Low High Low Low DNI DNI POP POP
PRU0 MII0 Ethernet Add-on Connector
N/A HSEC
CPSW RGMII2 Not Connected
PRU1 MII1 On-board PHY 4 Low Low High Low High DNI DNI POP POP
CPSW RGMII2 Ethernet Add-on Connector
N/A HSEC
PRU0 MII0 Not Connected
PRU0 MII0 On-board PHY 5 Low High Low Low X POP X DNI X
N/A Ethernet Add-on Connector
PRU1 MII1 HSEC
CPSW RGMII2 Not Connected
CPSW RGMII2 On-board PHY 6 Low High Low High X POP X DNI X
N/A Ethernet Add-on Connector
PRU1 MII1 HSEC
PRU0 MII0 Not Connected
N/A On-board PHY 7 Low High High X Low X DNI DNI POP
PRU0 MII0 Ethernet Add-on Connector
PRU1 MII1 HSEC
CPSW RGMII2 Not Connected
N/A On-board PHY 8 Low High High X High X DNI DNI POP
CPSW RGMII2 Ethernet Add-on Connector
PRU1 MII1 HSEC
PRU0 MII0 Not Connected
N/A On-board PHY 9 High Low Low X Low X POP X DNI
PRU1 MII1 Ethernet Add-on Connector
PR_MII0 or RGMII2 HSEC
N/A Not Connected
PRU1 MII1 On-board PHY 10 High Low High Low X X DNI X POP
N/A Ethernet Add-on Connector
PR_MII0 or RGMII2 HSEC
N/A Not Connected
N/A On-board PHY 11 High High X X X X X X X
N/A Ethernet Add-on Connector
PR_MII0 or RGMII2 PR_MII1 HSEC
Not Connected