SPRUJ86C October 2023 – August 2024 AM263P2 , AM263P4 , AM263P4-Q1
The bootmode for the AM263Px is selected by a DIP switch (SW6) or the test automation header. The test automation header uses an I2C IO expansion buffer to drive the bootmode when PORz is toggled. The supported boot modes are as shown in Table 2-4.
Boot Mode/Peripheral | Boot Media/Host | Notes |
---|---|---|
QSPI(4S), 50MHz | Flash Memory | ROM configures OSPI controller in QSPI 4S mode and downloads image from external flash, supports UART fallback boot mode if any failures. |
UART | External Host | ROM configures UART0 with baud rate of 115200bps and downloads image from external PC terminal using x-modem protocol. |
QSPI(1S), 50MHz | Flash Memory | ROM configures OSPI controller in QSPI 1S mode and downloads image from external flash, supports UART fallback boot mode if any failures. |
OSPI(8S), 50MHz | Flash Memory | ROM configures OSPI controller in 8S mode and downloads image from external flash, supports UART fallback boot mode if any failures. |
xSPI (1S->8D) , 25MHz, SFDP | QSPI Flash / External Host | ROM configures OSPI controller in xSPI 8D mode ,Reads SFDP table for read command and downloads image from external flash, Flashes with SFDP are of JEDEC standard Rev D only supported. |
DevBoot | N/A | No SBL. Used for development purposes only. |
Boot Mode | SPI0_D0_pad (SOP3) | SPI0_CLK_pad (SOP2) | OSPI_D1 (SOP1) | OSPI_D0 (SOP0) |
---|---|---|---|---|
QSPI(4S), 50MHz | 0 | 0 | 0 | 0 |
UART | 0 | 0 | 0 | 1 |
QSPI(1S), 50MHz | 0 | 0 | 1 | 0 |
OSPI(8S), 50MHz | 0 | 0 | 1 | 1 |
xSPI (1S->8D) , 25MHz, SFDP | 1 | 1 | 0 | 0 |
DevBoot | 1 | 0 | 1 | 1 |
Unsupported Boot Mode | All other combinations not defined above. |