SPRUJ86C October   2023  – August 2024 AM263P4 , AM263P4-Q1

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1Evaluation Module Overview
    1. 1.1 Introduction
      1.      Preface: Read This First
        1. 1.1.1.1 Sitara MCU+ Academy
        2. 1.1.1.2 Important Usage Notes
    2. 1.2 Kit Contents
    3. 1.3 Device Information
      1. 1.3.1 HSEC 180-pin Control Card Docking Station
      2. 1.3.2 Security
  6. 2Hardware
    1. 2.1  Component Identification
    2. 2.2  Power Requirements
      1. 2.2.1 Power Input Using USB Type-C Connector
      2. 2.2.2 Power Status LEDs
      3. 2.2.3 Power Tree
      4. 2.2.4 Power Sequence
      5. 2.2.5 PMIC
    3. 2.3  Functional Block Diagram
    4. 2.4  Reset
    5. 2.5  Clock
    6. 2.6  Boot Mode Selection
    7. 2.7  JTAG Path Selection
    8. 2.8  Header Information
    9. 2.9  GPIO Mapping
    10. 2.10 Push Buttons
    11. 2.11 Interfaces
      1. 2.11.1  Memory Interface
        1. 2.11.1.1 OSPI/QSPI
        2. 2.11.1.2 Board ID EEPROM
      2. 2.11.2  Ethernet Interface
        1. 2.11.2.1 Control Card Ethernet Routing
        2. 2.11.2.2 On Board Ethernet PHY
        3. 2.11.2.3 LED Indication in RJ45 Connector
        4. 2.11.2.4 Ethernet Add On Board Connector
      3. 2.11.3  I2C
      4. 2.11.4  Industrial Application LEDs
      5. 2.11.5  SPI
      6. 2.11.6  UART
      7. 2.11.7  MCAN
      8. 2.11.8  FSI
      9. 2.11.9  JTAG
      10. 2.11.10 Test Automation Header
      11. 2.11.11 LIN
      12. 2.11.12 MMC
      13. 2.11.13 ADC and DAC
    12. 2.12 HSEC Pinout and Pinmux Mapping
  7. 3Hardware Design Files
  8. 4Additional Information
    1. 4.1 If You Need Assistance
    2. 4.2 Trademarks
  9. 5Related Documentation
    1. 5.1 Supplemental Content
      1.      5.1.A E1 Board Modifications
      2.      5.1.B E2 Design Changes
      3.      5.1.C A Design Changes
  10. 6References
    1. 6.1 Reference Documents
    2. 6.2 Other TI Components Used in This Design
  11. 7Revision History
  12. 8Revision History

2.4 Reset

Figure 2-10 shows the reset architecture of the AM263Px Control Card.

AM263P1, AM263P1-Q1, AM263P2, AM263P2-Q1, AM263P4, AM263P4-Q1 Reset Architecture Figure 2-10 Reset Architecture

The AM263Px SoC has the following resets:

  • PORz is the Power-On-Reset for the MAIN Domain.
  • WARMRESETn is the Warm Reset to MAIN Domain.
AM263P1, AM263P1-Q1, AM263P2, AM263P2-Q1, AM263P4, AM263P4-Q1 PORz Reset Signal Tree Figure 2-11 PORz Reset Signal Tree

The PORz signal is driven by a 3-input AND gate that generates a power on reset for the MAIN domain when:

  • The PMIC drives the NRES, MCU Reset output signal low.
  • The 1.2V buck regulator outputs a low signal for the power good signal.
  • The user push button (SW10) is pressed.
  • The Test Automation Header outputs a logic LOW signal (TA_PORZn) to a P-Channel MOSFET gate which causes V_GS of the PMOS to be less than zero and so the PORz signal connects to the PMOS drain which is tied directly to ground.

The PORz signal is tied to:

  • AM263Px SoC PORz input
  • OSPI Flash Reset
  • On-board Gigabit Ethernet PHY reset
  • Ethernet add-on board connector
  • BOOTMODE buffer output enable
  • High-Speed Edge Connector (HSEC)

AM263P1, AM263P1-Q1, AM263P2, AM263P2-Q1, AM263P4, AM263P4-Q1 WARMRESETn Reset Signal Tree Figure 2-12 WARMRESETn Reset Signal Tree

The WARMRESETn signal creates a warm reset to the MAIN domain when:

  • The user push button (SW12) is pressed.
  • The Test Automation Header outputs a logic LOW signal (TA_RESETz) to a P-Channel MOSFET gate which causes V_GS of the PMOS to be less than zero and so the RESETz signal connects to the PMOS drain which is tied directly to ground.

The WARMRESETn signal is tied to:

  • AM263Px SoC WARMRESETN output
  • RESETz signal created from push button + PMOS logic
  • IO Expander reset
  • Micro SD reset
  • HSEC

The AM263Px Control Card also has an external interrupt to the SoC, INTn, that occurs when:

  • The user push button (SW11) is pressed.
  • The Test Automation Header outputs a logic LOW signal (TA_GPIO1) to a P-Channel MOSFET gate which causes V_GS of the PMOS to be less than zero and so the INTn signal connects to the PMOS drain which is tied directly to ground.