SPRUJ90B March 2023 – February 2024
Connectors | |
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J1 | Emulation/UART connector/Power - USB-C connector used to provide XDS110 emulation and USB-to-UART (SCI) communication through MSP432 logic. S1 determines which connections are enabled to the MCU. The USB-C connector also provides power on the controlCARD. |
J2 | microSD card slot – connects to MCU via SPI |
J3 | FSI Header |
J4 | Type C USB Connector - Data Peripheral to MCU |
J5 | EtherCAT P0 – RJ45 connector |
J6 | EtherCAT P1 – RJ45 connector |
LEDs | |
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D1 | Turns on when JTAG logic is powered on (green) |
D2 | Turns on (red) when 5V is
supplied to the controlCARD (5V can be supplied either through the USB-C connector or externally through the HSEC connector) |
D3 | Controlled by GPIO31 with negative logic (red) |
D4 | Controlled by GPIO34 with negative logic (red) |
D5 | JTAG/UART RX toggle indicator (blue) |
D6 | JTAG/UART TX toggle indicator (blue) |
D7 | Turns on (green) when 3.3V is supplied to the controlCARD from the on-board DC-DC (U3) |
D8 | Controlled by GPIO–145, EtherCAT Error LED (red) |
D9 | Controlled by GPIO–146, EtherCAT Run LED (green) |
Resistors and Capacitors | |
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R172-R195 | ADC RC input filter resistors: Series resistors which can be used to create an RC filter on the ADC's input. |
C128-C151 | ADC RC input filter capacitors: Optional capacitors, not populated by default, for the RC filter of the ADC input. |
Switches | ||||
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S1 | Isolated emulation and UART communication enable switches: | |||
S1 Position 1 – USB
JTAG Enable:
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S1 Position 2 – USB
UART communication enable:
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S2 |
Note: Watchdog output is disabled (default). To enable watchdog
functionality over S2, populate R55.
Enable/Disable watchdog Timer & adjustable programmable delay: S2 : Position 1 – SET 0 | Position 2 - SET 1 with CWD = 10kΩ (default) |
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tWDL - window watchdog lower boundary | SET 0 | SET 1 | Timing Setup | |
0 | 0 | 7.65 < tWDL < 10.35ms | ||
0 | 1 | |||
1 | 0 | Watchdog disabled | ||
1 (default) | 1 (default) | 1.48 < tWDL < 2.22ms |
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tWDU - window watchdog upper boundary | 0 |
0 |
92.7 < tWDU < 125.4ms |
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0 | 1 | 165.8 < tWDU < 224.3ms | ||
1 | 0 | Watchdog disabled | ||
1 (default) | 1 (default) | 9.35 < tWDU < 12.65ms | ||
Note: For additional hardware configurations,
see TPS3850 Precision voltage Supervisory
with Programmable Window Watchdog Timer data
sheet.
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S3 | Boot Mode Switch: Controls the Boot Options of the F28P65x device, see Table 6-6. For a full description, see the device specific data sheet. | |||
S4 | Reset switch: Switch connected to the XRSn line of the F28P65x device. Pressing this button pulls the device reset low. | |||
S5 |
ADC VREFHI Control Switch for ADC modules B & C: S5 Position 1 (lower switch) - VREFHI Control Switch for ADC module C:
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S5 Position 2 (upper switch) - VREFHI Control Switch for ADC module B:
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S6 |
ADC VREFHI Control Switch for ADC modules A and selection of external voltage reference: S6 Position 1 (lower switch) - VREFHI Control Switch for ADC module A:
CAUTION:
The reference pins, VREFHIA to VREFHIC and VREFLOA to VREFLOC, can be used to supply an external voltage reference to the associated ADCs. VREFHIA can also be used to supply the voltage reference to DAC A, and VREFHIB can be used to supply the voltage reference to DAC C. An internal voltage reference is available and connects to VREFHIA. To use the internal voltage reference on ADC B, ADC C or DAC C, connect VREFHIA to VREFHIB and/or VREFHIC externally.
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S6 Position 2 (upper switch) - External VREFHI Control Switch for all ADC modules:
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Test Points | |
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TP1 | USB 5V input: This is the 5V supply from the USB-C connector |
TP2 | Unfiltered 3.3V: Provides power to the MSP432 device |
TP3 | USB GND input: This GND from the USB-C connector |
TP4 | HSEC 5V input: 5V input provided to the controlCARD |
TP5 | Unfiltered 3.3V: This is the 3.3V rail from the DC-DC converter |
TP6 | Filtered 3.3V: Provides power to the F28P65x device |
TP7 | Filtered 1.2V: VDD core supply to the F28P65x device. Note that this controlCARD has been designed to use the external voltage regulator by default. The internal voltage regulator can be also enabled by removing R46 and populating R48 |
TP8 | Device Ground |
TP9 | 5V input: Output of the power selection switch |
TP10 | XRSn of F28P65X device: Connected to the XRSn pin of the F28P65x device |
TP11 | ERRORSTS: Error status output |
Mode | Switch Position 1 (left switch, GPIO72) | Switch Position 2 (right switch, GPIO84) | Boot From |
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00 | 0 (down) | 0 (down) | Parallel I/O |
01 | 0 (down, default) | 1 (up, default) | SCI / Wait Boot |
02 | 1 (up) | 0 (down) | CAN |
03 | 1 (up) | 1 (up) | Flash / USB |