SPRUJA3 November   2024 F29H850TU , F29H859TU-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Feature Differences Between F2837x, F2838x, F28P65x and F29H85x
    1. 1.1 F28x to F29x Feature Change Overview
  5. 2C29x Architecture
    1. 2.1 C29x Architecture Overview
      1. 2.1.1 Peripheral Interrupt Priority and Expansion (PIPE)
      2. 2.1.2 Safety and Security Module (SSU)
      3. 2.1.3 Real-Time DMA (RTDMA)
      4. 2.1.4 Lock-step Compare Module (LCM)
    2. 2.2 C28x vs C29x Architecture Overview
  6. 3PCB Design Consideration
    1. 3.1 VSSOSC
    2. 3.2 JTAG
    3. 3.3 VREF
  7. 4Feature Differences for System Consideration
    1. 4.1 New Features in F29H85x
      1. 4.1.1  Analog Subsystem
      2. 4.1.2  Data Logger and Trace (DLT)
      3. 4.1.3  Single Edge Nibble Transmission (SENT)
      4. 4.1.4  Waveform Analyzer Diagnostic (WADI)
      5. 4.1.5  EPWM
      6. 4.1.6  Bootrom
      7. 4.1.7  ERAD
      8. 4.1.8  XBAR
      9. 4.1.9  Error Signaling Module (ESM)
      10. 4.1.10 Error Aggregator
      11. 4.1.11 Hardware Security Module (HSM)
        1. 4.1.11.1 Cryptographic Accelerators
      12. 4.1.12 Safe Interconnect End-to-End (E2E) Safing
      13. 4.1.13 Critical MMR Safing With Parity
      14. 4.1.14 LPOST
    2. 4.2 Communication Module Changes
    3. 4.3 Control Module Changes
    4. 4.4 Analog Module Differences
    5. 4.5 Power Management
      1. 4.5.1 VREGENZ
      2. 4.5.2 Power Consumption
    6. 4.6 Memory Module Changes
    7. 4.7 GPIO Multiplexing Changes
  8. 5Software Development with F29H85x
    1. 5.1 Migration Report Generation Tool
  9. 6References

4.1.14 LPOST

F29H85x introduces the Logic Power-On Self-Test (LPOST) which addresses the start-up logic self-test requirements for functional safety applications. Coverage is configurable (60%, 80%, 90%) based on the application requirements. The higher the coverage required, the higher will be the impact on boot time. The LPOST test is triggered through software on power-up and/or during functional operation. Once the test is initiated, the device will enter scan test mode, perform the logic self-test, logs the status of the test, enter functional mode and issue a chip to reset. The reset issued after LPOST clears up any random data shifted in by the scan operation.

For power-on self-test, application code does not need to invoke the test. The test will be invoked by the Boot-ROM based on the OTP configuration. Upon completion of the boot process and test status, the application needs to take the appropriate safety action.

Note: All analog modules (except the ones required for the POST execution) shall be powered down during test.