SPRUJA3 November   2024 F29H850TU , F29H859TU-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Feature Differences Between F2837x, F2838x, F28P65x and F29H85x
    1. 1.1 F28x to F29x Feature Change Overview
  5. 2C29x Architecture
    1. 2.1 C29x Architecture Overview
      1. 2.1.1 Peripheral Interrupt Priority and Expansion (PIPE)
      2. 2.1.2 Safety and Security Module (SSU)
      3. 2.1.3 Real-Time DMA (RTDMA)
      4. 2.1.4 Lock-step Compare Module (LCM)
    2. 2.2 C28x vs C29x Architecture Overview
  6. 3PCB Design Consideration
    1. 3.1 VSSOSC
    2. 3.2 JTAG
    3. 3.3 VREF
  7. 4Feature Differences for System Consideration
    1. 4.1 New Features in F29H85x
      1. 4.1.1  Analog Subsystem
      2. 4.1.2  Data Logger and Trace (DLT)
      3. 4.1.3  Single Edge Nibble Transmission (SENT)
      4. 4.1.4  Waveform Analyzer Diagnostic (WADI)
      5. 4.1.5  EPWM
      6. 4.1.6  Bootrom
      7. 4.1.7  ERAD
      8. 4.1.8  XBAR
      9. 4.1.9  Error Signaling Module (ESM)
      10. 4.1.10 Error Aggregator
      11. 4.1.11 Hardware Security Module (HSM)
        1. 4.1.11.1 Cryptographic Accelerators
      12. 4.1.12 Safe Interconnect End-to-End (E2E) Safing
      13. 4.1.13 Critical MMR Safing With Parity
      14. 4.1.14 LPOST
    2. 4.2 Communication Module Changes
    3. 4.3 Control Module Changes
    4. 4.4 Analog Module Differences
    5. 4.5 Power Management
      1. 4.5.1 VREGENZ
      2. 4.5.2 Power Consumption
    6. 4.6 Memory Module Changes
    7. 4.7 GPIO Multiplexing Changes
  8. 5Software Development with F29H85x
    1. 5.1 Migration Report Generation Tool
  9. 6References

2.2 C28x vs C29x Architecture Overview

C29x as a new generation CPU, there are several improvements made in architectures, which has enhanced on the efficiency and the overall performance when executing instructions. Table 2-5 shows the organized improvement in C29x. For more detailed CPU information, please refer to C2000 C29x CPU and Instruction Set.

Table 2-5 C29x Improvement
Category C28x C29x
Architecture
  • 16-bit addressable
  • FPU32, FPU64
  • TMU32
  • NLPID
  • Fast Integer Division
  • 1x 32-bit program bus
  • 1x 32-bit read bus
  • 1x 32-bit write bus
  • Very Long Instruction Word architecture (VLIW)
  • Byte-addressable
  • FPU32, FPU64 (CPU3 only)
  • TMU32, TMU64 (CPU3 only)
  • NLPID
  • Fast Integer Division
  • 1x 128-bit program bus
  • 2x 64-bit read bus
  • 1x 64-bit write bus
Parallelism
  • 1 instruction per cycle
  • Protected pipeline (not extended to co-processors)
  • Up to 8 instructions per cycle
  • Fully protected pipeline
Performance - CPU running at same frequency:
  • 2x to 3x signal chain performance increase (motor control, power control)
  • 5x faster FFT performance (system diagnostics, system tuning, arc detection)
  • 4x faster interrupt response and reduced latency (support for real time interrupts)
  • 2x to 3x improvement in general purpose code (if then else, command processing)
Interrupt
  • Peripheral Interrupt Expansion (PIE)
  • INT, NMI
  • Real time interrupt latency: 40+ cycles
  • Peripheral Interrupt Priority and Expansion (PIPE)
  • INT, RTINT, NMI
  • Interrupt latency: 11 cycles
  • Dedicated HW stack for real-time interrupt
    • HW saves/restores the context
Security
  • Dual Code Security Module (DCSM)
  • Safety and Security Unit (SSU)
  • Hardware Security Module (HSM)
Safety
  • ASIL B
  • MPOST
  • ASIL D
  • MPOST, LPOST
  • ECC / Parity protection for bus and registers
  • MPU-like SSU enables freedom from interference enabled