SPRUJA3 November   2024 F29H850TU , F29H859TU-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Feature Differences Between F2837x, F2838x, F28P65x and F29H85x
    1. 1.1 F28x to F29x Feature Change Overview
  5. 2C29x Architecture
    1. 2.1 C29x Architecture Overview
      1. 2.1.1 Peripheral Interrupt Priority and Expansion (PIPE)
      2. 2.1.2 Safety and Security Module (SSU)
      3. 2.1.3 Real-Time DMA (RTDMA)
      4. 2.1.4 Lock-step Compare Module (LCM)
    2. 2.2 C28x vs C29x Architecture Overview
  6. 3PCB Design Consideration
    1. 3.1 VSSOSC
    2. 3.2 JTAG
    3. 3.3 VREF
  7. 4Feature Differences for System Consideration
    1. 4.1 New Features in F29H85x
      1. 4.1.1  Analog Subsystem
      2. 4.1.2  Data Logger and Trace (DLT)
      3. 4.1.3  Single Edge Nibble Transmission (SENT)
      4. 4.1.4  Waveform Analyzer Diagnostic (WADI)
      5. 4.1.5  EPWM
      6. 4.1.6  Bootrom
      7. 4.1.7  ERAD
      8. 4.1.8  XBAR
      9. 4.1.9  Error Signaling Module (ESM)
      10. 4.1.10 Error Aggregator
      11. 4.1.11 Hardware Security Module (HSM)
        1. 4.1.11.1 Cryptographic Accelerators
      12. 4.1.12 Safe Interconnect End-to-End (E2E) Safing
      13. 4.1.13 Critical MMR Safing With Parity
      14. 4.1.14 LPOST
    2. 4.2 Communication Module Changes
    3. 4.3 Control Module Changes
    4. 4.4 Analog Module Differences
    5. 4.5 Power Management
      1. 4.5.1 VREGENZ
      2. 4.5.2 Power Consumption
    6. 4.6 Memory Module Changes
    7. 4.7 GPIO Multiplexing Changes
  8. 5Software Development with F29H85x
    1. 5.1 Migration Report Generation Tool
  9. 6References

4.1.6 Bootrom

For bootrom differences between F28P65x and F29H85x see Table 4-2.

Table 4-2 Bootrom Comparison
Module F28P65x F29H85x
ROM Memory Standard and secure bootrom Start at 0x00000000 and is divided into Reset vector, NMI vector, LINK0, User tables and LINK1
Security Module DCSM initialization done through dummy reads SSU initialization, no dummy reads
MPOST Can execute at 150MHz, 75MHz PLL output clock as well as INTOSC clock MPOST and LPOST are performed by HSM and not by CPU1
PLL Option to enable/disable PLL during bootrom execution PLL is enabled by HSM, and CPU1 runs at PLL clock
Watchdog Timer Disabled by default Enabled by default
Error Status Pin GPIO configured as Error Status Pin GPIO configured as Error Status Pin and ESM configuration to influence error status pin
Peripheral Bootloaders Executed at bypass clock Executed at PLL clock
Peripheral Boot Modes Supported CAN, MCAN, I2C, SPI, SCI, USB, GPIO CAN, MCAN, I2C, SPI, UART-HS, GPIO
Critical Trim Loading Method Bootrom loads Hardware CTL module loads
Bootload Image Format Key followed by image data organized into blocks X509 certificate followed by the image data
Boot Process Involves downloading of image from peripheral Involves handshaking with HSM for X509 certificate and image sharing with HSM for integrity check or authentication
IPC IPC is based on C2000 IPC interface IPC between CPU1 and HSM is heterogeneous involving C2000 IPC interface on CPU1 and Mailbox based interface on HSM
NMI NMI is enabled at a later point in the boot flow NMI is enabled by default throughout the boot flow
OTP Single user OTP available Dual SECCFG sectors are available
Lockstep Lockstep is disabled during boot flow Lockstep is enabled during boot flow