As the whole architecture, RAM and FLASH memories have changed from F28P65x and F29H85x. Table 4-7 summarizes the memory features including error-checking and security assignment, and the different modes in flash.

In F29H85x, the architecture of the memory has changed. Every memory can be accessed by every CPU, but there are categorized and optimized sections of the RAM for better efficiency. There are program-optimized sections, LPAx and CPAx, while LPAx is optimized for CPU1/CPU2 and CPAx is optimized for CPU1/CPU3. Similarly, there are data-optimized sections with CPU1/CPU2 optimized (LDAx) and CPU1/CPU3 optimized (CDAx). In F28P65x, there is message RAM, and you do not see message RAM in F29H85x, but any memory can be used as CPU message RAM in our new device. It can be created out of the RAMS along with SSU.

The 128-bit memory controller enables zero wait states on program accesses. This allows data accesses, providing the ability to copy code, download code, and insert software breakpoints, which also utilize maximum parallelism of the CPU. The 64-bit LDx and CDx memory controller is similar to the 128-bit LPx and CPx memory controller, but the 64-bit memory controller has zero wait states on data access and one wait state on program access. Furthermore, RTDMA is connected through a slow access port, so all accesses are minimum one wait state. With RTDMA burst support, RTDMA supports local address generation within the MEMSS memory controller. This enables performance close to zero wait states.

The atomic operations support in memory module is also an main improvement in F29H85x. Atomic operation executes a protected sequence of memory operations while preventing other memory initiators from interrupting. This sequence can involve reading and updating shared variables in memory, where there is a need to protect these variables from updates by other initiators, which means in multiple sequences, you need to set as atomic so that they can finish the access first and cannot be interrupted. Note that all RAMs have ECC protection with a 32-bit granularity. This means that every 32 bits has 7 bits of ECC.

In flash, there are 4 modes that you can choose from. It depends on how you want to allocate the flash with difference CPUS and whether you will need FOTA. Table 4-9 shows the different modes and how each of the solutions could be used.