The SoC power is typically considered
to have two different components – dynamic power and leakage.(2)
- The dynamic power is computed
based upon two numbers for the IP – max power and idle power (both scaled to
the voltage). The dynamic power is computed as the weighted average of the
max and idle power:
Pdyn=Pmax×Utilization+Pidle×(1-Utilization)
- For background:
Dynamic power is typically computed as fCV². Consider a clock signal
on a pcb that is driven from a CMOS output to a CMOS input. Dynamic
power is computed based upon the (a) frequency of the signal – f;
(b) the capacitance of the input load and the pcb trace capacitance
– C; and (c) the voltage swing of the signal – V.
- Within the tool, the
user can select the frequency for some IP as well as the IP’s
utilization. The frequency and utilization are obviously linked; as
the frequency decreases, the utilization will need to increase to
maintain the same activity. Therefore, a function that requires 40%
loading on an IP will have nearly the same power if the frequency is
cut in half and the utilization doubles to 80%.
- The leakage power is computed
based upon voltage, junction temperature, and manufacturing process
variation. While the process and voltage have strong effects on the leakage
power, the leakage power increases exponentially with Tj.
- For background, a
CMOS transistor is considered to have two states: (a) ON in which
the channel between source and drain is conducting; and (b) OFF in
which the channel is non-conductive between the source and the
drain. Leakage power arises because the OFF state can allow a
trickle of current to cross the channel.