SPRUJE4A August   2024  – November 2024 F29H850TU , F29H859TU-Q1

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   5
  6. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  7. 2Hardware
    1. 2.1  Quick Start Setup
      1. 2.1.1 Configuration 1: Stand-alone Configuration
      2. 2.1.2 Configuration 2: C2000 controlCARD Backward Compatibility Configuration
      3. 2.1.3 Configuration 3: Baseboard Configuration
    2. 2.2  Design Details
      1. 2.2.1 Power Tree
      2. 2.2.2 Clocking
      3. 2.2.3 Reset
      4. 2.2.4 Board ID EEPROM
    3. 2.3  Power Requirements
    4. 2.4  Configuration Options
      1. 2.4.1 Boot Mode Selection
      2. 2.4.2 ADC Voltage Reference Selection
      3. 2.4.3 MCAN-A Boot Support
      4. 2.4.4 FSI DLT Support
      5. 2.4.5 EtherCAT PHY Clock Selection
    5. 2.5  Header Information
      1. 2.5.1 Baseboard Headers (J1, J2, J3)
      2. 2.5.2 XDS Debug Header (J4)
      3. 2.5.3 DLT Header (J5)
    6. 2.6  Push Buttons
    7. 2.7  User LEDs
    8. 2.8  Debug Information
    9. 2.9  Test Points
    10. 2.10 Best Practices
  8. 3Software
    1. 3.1 Software Description
    2. 3.2 Software Installation
    3. 3.3 Software Development
    4. 3.4 Developing an Application
  9. 4Hardware Design Files
    1. 4.1 Schematics
    2. 4.2 PCB Layouts
    3. 4.3 Bill of Materials (BOM)
  10. 5Additional Information
    1. 5.1 Known Hardware or Software Issues
      1. 5.1.1 EVM Usage Notes
      2. 5.1.2 MCU144E1 Known Hardware Issues
    2. 5.2 Trademarks
  11. 6References
  12. 7Revision History

5.1.1 EVM Usage Notes

Parallel I/O Boot Can Cause Watchdog Timer Timeout if No Host Is Connected to EVM

Revisions Affected: All

Use of parallel I/O boot can lead to a watchdog timer timeout if a host does not drive the host control lines. The timeout will cause the F29H85x device to reset.

The boot mode switch (S1) on the EVM should not be set to parallel I/O boot unless a host is present to drive the host control lines.

Refer to the F29H85x and F29P58x Real-Time Microcontrollers Technical Reference Manual for more information on parallel boot.

Device GPIOs Dedicated to PMIC SPI Bus Should Be Used for SPI Function If Used On Baseboard

Revisions Affected: All

The F29H85x device and the PMIC on the controlSOM are connected via SPI bus. The SPI bus is used by the device to configure the PMIC and also, when enabled, to service the PMIC's watchdog. The SPI bus GPIOs are also connected to the SPI standard location on J1, see Table 5-1 for more information. Note that the SPI_STE pin is not connected to any of the baseboard headers.

Care must be taken when using these GPIOs on a baseboard since these GPIOs will toggle when the F29H85x device communicates with the PMIC via SPI. It is recommended to always use these pins for SPI function on a baseboard.

Table 5-1 PMIC SPI Bus GPIOs

SPI Pin

GPIO

J1 Connection

PICO

GPIO91

J1.75

POCI

GPIO92

J1.77

CLK

GPIO93

J1.79

PTE

GPIO94

Not connected to J1

Limited Functionality On Early EVM Revisions

Revisions Affected: MCU144E1-001

Initial builds of the F29H85X-SOM-EVM are assembled with early samples of the F29H85x microcontroller (MCU). These MCU samples have the following limitations:

  • Flash is not supported: early F29H85x devices do not support internal flash. All microcontroller code must be loaded to and executed from internal RAM.
  • Incorrect package marking: early F29H85x devices have an incorrect package label. The correct package label is F29H850TU9.
  • Internal oscillator (INTOSC2) defaults to 6MHz: in early F29H85x devices INTOSC2 is untrimmed and defaults to 6MHz.
F29H85X-SOM-EVMs built with these early F29H85x MCU samples are labeled as MCU144E1-001.