SPRUJF4A October   2024  – December 2024

 

  1.   1
  2.   Description
  3.   Features
  4.   Applications
  5.   5
  6. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
    5.     General Texas Instruments High Voltage Evaluation (TI HV EVM) User Safety Guidelines
  7. 2Hardware
    1. 2.1 Hardware Description
      1. 2.1.1 Auxiliary Power Supply
      2. 2.1.2 DC Link Voltage Sensing
      3. 2.1.3 Motor Phase Voltage Sensing
      4. 2.1.4 Motor Phase Current Sensing
        1. 2.1.4.1 Three-Shunt Current Sensing
        2. 2.1.4.2 Single-Shunt Current Sensing
      5. 2.1.5 External Overcurrent Protection
      6. 2.1.6 Internal Overcurrent Protection for TMS320F2800F137
    2. 2.2 Getting Started Hardware
      1. 2.2.1 Test Conditions and Equipment
      2. 2.2.2 Test Setup
  8. 3Motor Control Software
    1. 3.1 Three-Phase PMSM Drive System Design Theory
      1. 3.1.1 Field-Oriented Control of PMSM
        1. 3.1.1.1 Space Vector Definition and Projection
          1. 3.1.1.1.1 ( a ,   b ) ⇒ ( α , β ) Clarke Transformation
          2. 3.1.1.1.2 ( α , β ) ⇒ ( d ,   q ) Park Transformation
        2. 3.1.1.2 Basic Scheme of FOC for AC Motor
        3. 3.1.1.3 Rotor Flux Position
      2. 3.1.2 Sensorless Control of PM Synchronous Motor
        1. 3.1.2.1 Enhanced Sliding Mode Observer With Phase-Locked Loop
          1. 3.1.2.1.1 Mathematical Model and FOC Structure of an IPMSM
          2. 3.1.2.1.2 Design of ESMO for the IPMS
            1. 3.1.2.1.2.1 Rotor Position and Speed Estimation With PLL
      3. 3.1.3 Field Weakening (FW) and Maximum Torque Per Ampere (MTPA) Control
    2. 3.2 Getting Started Software
      1. 3.2.1 GUI
      2. 3.2.2 Download and Install C2000 Software
      3. 3.2.3 Using the Software
      4. 3.2.4 Project Structure
  9. 4Test Procedure and Results
    1. 4.1 Build Level 1: CPU and Board Setup
    2. 4.2 Build Level 2: Open-Loop Check With ADC Feedback
    3. 4.3 Build Level 3: Closed Current Loop Check
    4. 4.4 Build Level 4: Full Motor Drive Control
    5. 4.5 Test Procedure
      1. 4.5.1 Startup
      2. 4.5.2 Build and Load Project
      3. 4.5.3 Setup Debug Environment Windows
      4. 4.5.4 Run the Code
        1. 4.5.4.1 Build Level 1 Test Procedure
        2. 4.5.4.2 Build Level 2 Test Procedure
        3. 4.5.4.3 Build Level 3 Test Procedure
        4. 4.5.4.4 Build Level 4 Test Procedure
          1. 4.5.4.4.1 Tuning Motor Drive FOC Parameters
          2. 4.5.4.4.2 Tuning Field Weakening and MTPA Control Parameters
          3. 4.5.4.4.3 Tuning Current Sensing Parameters
    6. 4.6 Performance Data and Results
      1. 4.6.1 Load and Thermal Test
      2. 4.6.2 Overcurrent Protection by External Comparator
      3. 4.6.3 Overcurrent Protection by Internal CMPSS
  10. 5Hardware Design Files
    1. 5.1 Schematics
    2. 5.2 PCB Layouts
    3. 5.3 Bill of Materials (BOM)
  11. 6Additional Information
    1. 6.1 Known Hardware or Software Issues
    2. 6.2 Trademarks
    3. 6.3 Terminology
  12. 7References
  13. 8Revision History

External Overcurrent Protection

The TIEVM-MTR-HVINV implements two redundant overcurrent protection (OCP) circuits. First, an external comparator is capable of reporting an overcurrent fault to the 3-phase inverter. Second, the daughterboard MCU is capable of reporting an overcurrent fault through the use of internal comparators. If either OCP mechanism reports a fault, both the 3-phase inverter and the MCU transition into a fault state. The system remains in a fault state until the state is manually cleared.

Figure 2-12 shows the external OCP circuit. This circuit sums the three current phases, the compares that sum to a reference value. If the summation of the three phase currents ever exceeds the reference value, then the 'IPM_CIN' signal switches and the IPM reports an overcurrent fault to the microcontroller. The exact overcurrent protection current can be calculated by below equations.(1)

First, the reference voltage V- is generated via a voltage divider from the 3.3V power rail.

Equation 7. V-=3.3V×R108R107+R108=3.3V×1k20k+1k=0.15714V

Next, note that the resistance from any IPM phase to the junction point U10+ is 5.12kΩ. In this scenario, two of the phases (for example, V and W) are at approximately 0A, while the third phase (U) is experiencing a current spike and triggering the OCP circuit. As such, consider RV and Rw in parallel.

Equation 8. RU=RV=RW=R87+R8=5.12k
Equation 9. RV||W=1RV+1RW-1=25.12k-1=2.56k

The voltage at the junction point U10+ can be referred to as V+. V+ is generated via voltage division relative to the voltage of each phase of the IPM (VU, VV, VW). Note that VV and VW are both assumed to be 0V in this scenario, as IV and IW are both stated to be at or approaching 0A.

Equation 10. V + = ( V U - V VW ) × R V | | W R U + R V | | W = V U × R V | | W R U + R V | | W
Equation 11. V + = V U × R V | | W R U + R V | | W = V U × 2 . 56 k 5 . 12 k + 2 . 56 k = V U 3

VU is also defined as the Voltage across the shunt resistor Rshunt during the overcurrent event.

Equation 12. VU=Rshunt×IOCP=0.05×IOCP

For the OCP circuit to trigger, V+ must be greater than or equal to the reference voltage V-.

Equation 13. V+=0.05×IOCP3V-
Equation 14. IocpV-0.053=0.157140.053=9.42857A
TIEVM-MTR-HVINV External Overcurrent Protection CircuitFigure 2-12 External Overcurrent Protection Circuit

Certain revisions of the board may have higher OCP limits for the external circuit. In these instances, the internal (CMPSS) protection is still fully functional at the intended levels. Refer to Section 6.1 for more information.