SPRZ397K November   2012  – September 2024 TDA2EG-17 , TDA2HF , TDA2HG , TDA2HV , TDA2LF , TDA2SA , TDA2SG , TDA2SX

 

  1.   1
  2. 1Introduction
    1.     Related Documentation
    2.     Trademarks
    3.     Modules Impacted
  3. 2Silicon Advisories
    1.     Revisions SR 2.0, 1.1, 1.0 - Advisories List
    2.     i202
    3.     i378
    4.     i631
    5.     i694
    6.     i698
    7.     i699
    8.     i727
    9.     i729
    10.     i734
    11.     i767
    12.     i782
    13.     i783
    14.     i802
    15.     i803
    16.     i807
    17.     i808
    18.     i809
    19.     i810
    20.     i813
    21.     i814
    22.     i815
    23.     i818
    24.     i819
    25.     i820
    26.     i824
    27.     i826
    28.     i829
    29.     i834
    30.     i837
    31.     i840
    32.     i841
    33.     i842
    34.     i843
    35.     i847
    36.     i849
    37.     i852
    38.     i854
    39.     i855
    40.     i856
    41.     i859
    42.     i861
    43.     i862
    44.     i863
    45.     i868
    46.     i869
    47.     i870
    48.     i871
    49.     i872
    50.     i874
    51.     i875
    52.     i878
    53.     i879
    54.     i880
    55.     i882
    56.     i883
    57.     i884
    58.     i887
    59.     i889
    60.     i890
    61.     i893
    62.     i895
    63.     i896
    64.     i897
    65.     i898
    66.     i899
    67.     i900
    68.     i901
    69.     i903
    70.     i916
    71.     i927
    72.     i929
    73.     i930
    74.     i932
    75.     i933
    76.     i936
    77.     i940
    78.     i2446
  4. 3Silicon Limitations
    1.     Revisions SR 2.0, 1.1, 1.0 - Limitations List
    2.     i596
    3.     i641
    4.     i833
    5.     i838
    6.     i844
    7.     i845
    8.     i848
    9.     i850
    10.     i851
    11.     i853
    12.     i857
    13.     i858
    14.     i876
    15.     i877
    16.     i892
    17.     i909
  5. 4Silicon Cautions
    1.     Revisions SR 2.0, 1.1, 1.0 - Cautions List
    2.     i781
    3. 4.1 106
    4.     i827
    5.     i832
    6.     i836
    7.     i839
    8.     i864
    9.     i885
    10.     i886
    11.     i912
    12.     i926
    13.     i931
    14.     i935
  6. 5Revision History

i929

MMC1/2 SDR104/HS200 Mode DLL Delay Value May Result In Unexpected Tuning Pattern Errors

CRITICALITY

Low

DESCRIPTION

Internal to the MMC module, a second stage latch is used to recapture data captured by DLL delayed CLK, MMC_DLL_CLK. The second stage latch captures with the original transmitting clock, MMC_CLK.

 Simplified SoC 192-MHz Mode DLL Block DiagramFigure 2-2 Simplified SoC 192-MHz Mode DLL Block Diagram

MMC_DLL_CLK and MMC_CLK both run at the same clock frequency. This results in a narrow range of tuning ratio elements, where the delayed MMC_DLL_CLK comes in phase with MMC_CLK. If the clocks are in phase, the data captured by the first clock violates the setup and hold time requirements needed for the second stage latch, resulting in incorrectly read data. This is known as tuning re-timing errors.

For systems in which MMC DLL tuning algorithm* choses a ratio less than 40, which is sufficiently far from the lowest re-timing error ratio element, no workaround is necessary.

WORKAROUND

A DLL tuning algorithm has been implemented that can avoid the tuning re-timing errors. More details on this can be found in App Note SPRACA9. The following notes summarize the updated algorithm:

  1. Implement two stage tuning. The software begins with the regular tuning algorithm, using 4-step increments, to optimize boot time. When the initial ratio is chosen within the largest passing window, the software checks 10 tuning steps in each direction, using single steps, to identify whether the chosen ratio is at risk of a tuning re-timing error. If at risk, the value of the chosen ratio is adjusted to move away from the error. If not, the chosen ratio is used unchanged.
  2. Choose ratio based on temperature. Both tuning band errors and tuning re-timing errors shift with temperature. The software takes this dependency into consideration when selecting the tuning ratio element to use for functionality.

Note: NOTE: *Legacy MMC DLL tuning algorithm are algorithms that were implemented before errata i929 was published. These algorithms do not take temperature nor single step tuning into consideration and were only tuned with step size = 4.

REVISIONS IMPACTED

SR 2.0, 1.1, 1.0

TDA2x: 2.0, 1.1, 1.0

DRA75x, DRA74x: 2.0, 1.1, 1.0

AM572x: 2.0, 1.1