SPRZ397K November   2012  – September 2024 TDA2EG-17 , TDA2HF , TDA2HG , TDA2HV , TDA2LF , TDA2SA , TDA2SG , TDA2SX

 

  1.   1
  2. 1Introduction
    1.     Related Documentation
    2.     Trademarks
    3.     Modules Impacted
  3. 2Silicon Advisories
    1.     Revisions SR 2.0, 1.1, 1.0 - Advisories List
    2.     i202
    3.     i378
    4.     i631
    5.     i694
    6.     i698
    7.     i699
    8.     i727
    9.     i729
    10.     i734
    11.     i767
    12.     i782
    13.     i783
    14.     i802
    15.     i803
    16.     i807
    17.     i808
    18.     i809
    19.     i810
    20.     i813
    21.     i814
    22.     i815
    23.     i818
    24.     i819
    25.     i820
    26.     i824
    27.     i826
    28.     i829
    29.     i834
    30.     i837
    31.     i840
    32.     i841
    33.     i842
    34.     i843
    35.     i847
    36.     i849
    37.     i852
    38.     i854
    39.     i855
    40.     i856
    41.     i859
    42.     i861
    43.     i862
    44.     i863
    45.     i868
    46.     i869
    47.     i870
    48.     i871
    49.     i872
    50.     i874
    51.     i875
    52.     i878
    53.     i879
    54.     i880
    55.     i882
    56.     i883
    57.     i884
    58.     i887
    59.     i889
    60.     i890
    61.     i893
    62.     i895
    63.     i896
    64.     i897
    65.     i898
    66.     i899
    67.     i900
    68.     i901
    69.     i903
    70.     i916
    71.     i927
    72.     i929
    73.     i930
    74.     i932
    75.     i933
    76.     i936
    77.     i940
    78.     i2446
  4. 3Silicon Limitations
    1.     Revisions SR 2.0, 1.1, 1.0 - Limitations List
    2.     i596
    3.     i641
    4.     i833
    5.     i838
    6.     i844
    7.     i845
    8.     i848
    9.     i850
    10.     i851
    11.     i853
    12.     i857
    13.     i858
    14.     i876
    15.     i877
    16.     i892
    17.     i909
  5. 4Silicon Cautions
    1.     Revisions SR 2.0, 1.1, 1.0 - Cautions List
    2.     i781
    3. 4.1 106
    4.     i827
    5.     i832
    6.     i836
    7.     i839
    8.     i864
    9.     i885
    10.     i886
    11.     i912
    12.     i926
    13.     i931
    14.     i935
  6. 5Revision History

i863

MMC2 Has PU/PD Contention Immediately after Release from Reset

CRITICALITY

High

DESCRIPTION

On SR1.x, the MMC2_DAT[x] terminals have internal weak pull-down resistors (PD) in the range of 8 kΩ ~ 36 kΩ (1.8 V) or 9 kΩ ~ 82 kΩ (3.3 V) which are turned on by default immediately after the device has been released from reset. The JEDEC eMMC standard requires external weak pull-up resistors (PU) on eMMC CMD and DAT signals, and internal weak pull-up resistors on DAT[7-0] terminals of eMMC devices to prevent inputs from floating. The external resistors are in the range of 4.7 kΩ ~ 100 kΩ and the internal eMMC device resistors are in the range of 10 kΩ ~ 150 kΩ. After reset, these weak pull-up resistors contradict the internal pull state of the device and presents a PU/PD contention on the eMMC DAT signals; this may lead to reliability issues if not handled properly.

On SR2.x, the MMC2 DAT[x] terminals have internal weak pull-down resistors (PD) which are permanently disabled when SYSBOOT15=1 or enabled by default when SYSBOOT15=0. Refer to the TRM section “Permanent PU/PD disabling” for details.

PU/PD Contention Reliability Issue:

The PU/PD contention applies a mid-supply voltage to the input buffer which may cause excessive current to flow through the input buffer. In this scenario, both FETs (PMOS/NMOS) in the input buffer are partially turned ON, resulting in a current path from VDD through the input buffer to VSS. Total leakage power during this state may be up to 800 µA per input buffer operating at 1.8 V, or up to 2 mA per input buffer operating at 3.3 V. Hysteresis on the input buffers prevents the noise from causing the input logic level to change state, but it does not prevent the current path.

To maintain system reliability, SW should minimize the duration eMMC DAT lines spend in this invalid state.

WORKAROUND

SW should minimize the time eMMC DAT terminals spend in the PU/PD contention state to a maximum of 200 hours in a device life cycle.

On SR1.x, this is done by configuring MMC pinmux configuration to turn off the internal pull-down resistors as early as possible in secondary boot loader (SBL, i.e. the initial software image loaded by the device’s ROM boot loader; one that is responsible for loading subsequent boot images or the main OS). If external pulls are not implemented on the PCB, then the internal PU on eMMC DAT signals should be enabled simultaneously. Alternately, if external pulls are implemented (as recommended by the JEDEC JESD84- B451) the internal pull resistors can be disabled. SW should take care of writing the below values in the listed registers-bit fields:


CTRL_CORE_PAD_GPMC_A24[3:0] = 1   ; mmc2_dat0
CTRL_CORE_PAD_GPMC_A24[16] = 0    ; Enables weak Pull Up/Down
CTRL_CORE_PAD_GPMC_A24[17] = 1    ; Pull Up is selected
CTRL_CORE_PAD_GPMC_A24[18] = 1    ; Receive Mode is Enabled
CTRL_CORE_PAD_GPMC_A24[19] = 0    ; Fast slew is selected
CTRL_CORE_PAD_GPMC_A25[3:0] = 1   ; mmc2_dat1
CTRL_CORE_PAD_GPMC_A25[16] = 0    ; Enables weak Pull Up/Down
CTRL_CORE_PAD_GPMC_A25[17] = 1    ; Pull Up is selected
CTRL_CORE_PAD_GPMC_A25[18] = 1    ; Receive Mode is Enabled
CTRL_CORE_PAD_GPMC_A25[19] = 0    ; Fast slew is selected
CTRL_CORE_PAD_GPMC_A26[3:0] = 1   ; mmc2_dat2
CTRL_CORE_PAD_GPMC_A26[16] = 0    ; Enables weak Pull Up/Down
CTRL_CORE_PAD_GPMC_A26[17] = 1    ; Pull Up is selected
CTRL_CORE_PAD_GPMC_A26[18] = 1    ; Receive Mode is Enabled
CTRL_CORE_PAD_GPMC_A26[19] = 0    ; Fast slew is selected
CTRL_CORE_PAD_GPMC_A27[3:0] = 1   ; mmc2_dat3
CTRL_CORE_PAD_GPMC_A27[16] = 0    ; Enables weak Pull Up/Down
CTRL_CORE_PAD_GPMC_A27[17] = 1    ; Pull Up is selected
CTRL_CORE_PAD_GPMC_A27[18] = 1    ; Receive Mode is Enabled
CTRL_CORE_PAD_GPMC_A27[19] = 0    ; Fast slew is selected
CTRL_CORE_PAD_GPMC_A19[3:0] = 1   ; mmc2_dat4
CTRL_CORE_PAD_GPMC_A19 [16] = 0    ; Enables weak Pull Up/Down
CTRL_CORE_PAD_GPMC_A19 [17] = 1    ; Pull Up is selected
CTRL_CORE_PAD_GPMC_A19 [18] = 1    ; Receive Mode is Enabled
CTRL_CORE_PAD_GPMC_A19 [19] = 0    ; Fast slew is selected
CTRL_CORE_PAD_GPMC_A20[3:0] = 1   ; mmc2_dat5
CTRL_CORE_PAD_GPMC_A20[16] = 0    ; Enables weak Pull Up/Down
CTRL_CORE_PAD_GPMC_A20[17] = 1    ; Pull Up is selected
CTRL_CORE_PAD_GPMC_A20[18] = 1    ; Receive Mode is Enabled
CTRL_CORE_PAD_GPMC_A20[19] = 0    ; Fast slew is selected
CTRL_CORE_PAD_GPMC_A21[3:0] = 1   ; mmc2_dat6
CTRL_CORE_PAD_GPMC_A21[16] = 0    ; Enables weak Pull Up/Down
CTRL_CORE_PAD_GPMC_A21[17] = 1    ; Pull Up is selected
CTRL_CORE_PAD_GPMC_A21[18] = 1    ; Receive Mode is Enabled
CTRL_CORE_PAD_GPMC_A21[19] = 0    ; Fast slew is selected
CTRL_CORE_PAD_GPMC_A22[3:0] = 1   ; mmc2_dat7
CTRL_CORE_PAD_GPMC_A22[16] = 0    ; Enables weak Pull Up/Down
CTRL_CORE_PAD_GPMC_A22[17] = 1    ; Pull Up is selected
CTRL_CORE_PAD_GPMC_A22[18] = 1    ; Receive Mode is Enabled
CTRL_CORE_PAD_GPMC_A22[19] = 0    ; Fast slew is selected
			

The 200 hours can be distributed any way throughout the lifetime of a device, and can be one instance of 200 hours or any number of occurrences totaling 200 hours.

On SR2.x, if SYSBOOT15=1 then no software workaround is required since the internal pulls are permanently disabled. Note that external pull-up resistors on the MMC data bus are mandatory in this case. It is OK if the software workaround remains since accesses to configure the internal pulls has no effect.

REVISIONS IMPACTED

SR 1.1, 1.0

SR 2.0 (if SYSBOOT15=0, as described in i863 above)

TDA2x: 2.0, 1.1, 1.0

DRA75x, DRA74x: 2.0, 1.1, 1.0

AM572x: 2.0, 1.1