SPRZ397K November   2012  – September 2024 TDA2EG-17 , TDA2HF , TDA2HG , TDA2HV , TDA2LF , TDA2SA , TDA2SG , TDA2SX

 

  1.   1
  2. 1Introduction
    1.     Related Documentation
    2.     Trademarks
    3.     Modules Impacted
  3. 2Silicon Advisories
    1.     Revisions SR 2.0, 1.1, 1.0 - Advisories List
    2.     i202
    3.     i378
    4.     i631
    5.     i694
    6.     i698
    7.     i699
    8.     i727
    9.     i729
    10.     i734
    11.     i767
    12.     i782
    13.     i783
    14.     i802
    15.     i803
    16.     i807
    17.     i808
    18.     i809
    19.     i810
    20.     i813
    21.     i814
    22.     i815
    23.     i818
    24.     i819
    25.     i820
    26.     i824
    27.     i826
    28.     i829
    29.     i834
    30.     i837
    31.     i840
    32.     i841
    33.     i842
    34.     i843
    35.     i847
    36.     i849
    37.     i852
    38.     i854
    39.     i855
    40.     i856
    41.     i859
    42.     i861
    43.     i862
    44.     i863
    45.     i868
    46.     i869
    47.     i870
    48.     i871
    49.     i872
    50.     i874
    51.     i875
    52.     i878
    53.     i879
    54.     i880
    55.     i882
    56.     i883
    57.     i884
    58.     i887
    59.     i889
    60.     i890
    61.     i893
    62.     i895
    63.     i896
    64.     i897
    65.     i898
    66.     i899
    67.     i900
    68.     i901
    69.     i903
    70.     i916
    71.     i927
    72.     i929
    73.     i930
    74.     i932
    75.     i933
    76.     i936
    77.     i940
    78.     i2446
  4. 3Silicon Limitations
    1.     Revisions SR 2.0, 1.1, 1.0 - Limitations List
    2.     i596
    3.     i641
    4.     i833
    5.     i838
    6.     i844
    7.     i845
    8.     i848
    9.     i850
    10.     i851
    11.     i853
    12.     i857
    13.     i858
    14.     i876
    15.     i877
    16.     i892
    17.     i909
  5. 4Silicon Cautions
    1.     Revisions SR 2.0, 1.1, 1.0 - Cautions List
    2.     i781
    3. 4.1 106
    4.     i827
    5.     i832
    6.     i836
    7.     i839
    8.     i864
    9.     i885
    10.     i886
    11.     i912
    12.     i926
    13.     i931
    14.     i935
  6. 5Revision History

i864

VDDS18V to VDDSHVn Current Path

CRITICALITY

Medium

DESCRIPTION

A current path exists between vdds18v and vddshvn during power down sequence.

The Data Manual allows the vddshvn rail (in either 3.3V or 1.8V mode) to power down at the same time or before the vdds18v rail. When the vddshvn rail is powered down before the vdds18v rail, the vddshvn rail stays at Plateau Level (<1.5V) until the vdds18v rail is disabled, as shown in the waveform below.

A subset of the SOC's LVCMOS IOs (refer to DM for details) have a pull-up resistor that is active by default, including during reset and power-down. The SOC's IOs that have internal or external pull-ups will stay at Plateau Level (<1.5V) during the power-down. If other ICs on the board that are interfaced to the SOC's LVCMOS signals use a separate supply then it's possible that the other IC's signals can be pulled to the Plateau Level while its power supply is off.

 PAB_RevAFigure 4-1 PAB_RevA

The root cause of the plateau is related to the LVCMOS IO buffer Dual Voltage detection circuitry. The LVCMOS Dual Voltage IO includes voltage comparator circuitry to determine if the IO is in 3.3V mode or 1.8V mode. During powerdown of vddshvn domains, a current path in the internal bias transistors results in the vddshvn rail being held to an intermediate voltage level (<1.5 V). This path can consume at most 500 uA per IO - worst case estimate is ~150 mA (based on 280 IOs) from the vdds18v supply during power down. This path is not a reliability concern for the device.

The plateau is no concern for systems where the same supply/LDO is used for vddshvn rail and the other components that interface to the SOC's Dual Voltage LVCMOS IOs.

Systems that use independent supplies for the SOC rail and the other component's rail require further analysis by the system designer. There may be a state where SOC's IO's with internal or external pull-ups are pulled to plateau level (<1.5V) while the external device is powered down. In this case, the current on any given IO is limited due to the ~10 kOhm (minimum) internal pull-up resistor. The limit is 150 µA per IO (1.5 V maximum plateau / 10 kOhm minimum pull-up resistor.) Refer to the device Data Manual for details on which pins include a pull-up resistor by default.

GUIDELINES

In general, TI recommends using the same supply source for connected components. E.g., a single LDO should drive vddshvn and the related 3.3V external components.

For systems that use a different 3.3V supply for the SOC and connected ICs, customers should evaluate their system for reliability risk. If necessary, the PMIC OTP power-down sequence can be modified to delay the vddshv[11:1] powerdown to coincide with the vdds18v powerdown. [Note: The 3.3V rail must never be 2.0V above the 1.8V rail.]

VDDSHV8 is a special case. If VDDSHV8 is powered by the same LDO/switch as the other VDDSHVn rails then the VDDSHV8 rail can also be delayed. However, if the VDDSHV8 rail is supplied by a different LDO (e.g., LDO1 on EVM) than the other VDDSHVn rails, then the sequence should not be modified.

REVISIONS IMPACTED

SR 2.0, 1.1, 1.0

TDA2x: 2.0, 1.1, 1.0

DRA75x, DRA74x: 2.0, 1.1, 1.0

AM572x: 2.0, 1.1