SPRZ398K November 2012 – September 2024 DRA745 , DRA746 , DRA750 , DRA756
MSI Bit in PCIECTRL_TI_CONF_IRQSTATUS_MSI Register Does Not Clear Automatically
Low
The MSI bit in PCIECTRL_TI_CONF_IRQSTATUS_MSI register does not clear automatically even after all the vectors in PCIECTRL_PL_MSI_CTRL_INT_STATUS_N registers are cleared.
Software should manually clear PCIECTRL_TI_CONF_IRQSTATUS_MSI[4] MSI bit after making sure there are no vectors set in PCIECTRL_PL_MSI_CTRL_INT_STATUS_N registers. If MSI bit is cleared with some of the bits of PCIECTRL_PL_MSI_CTRL_INT_STATUS_N still set then those interrupts may be lost which may lead to non-functional remote endpoints.
Following is the recommended sequence for handling MSI interrupt to avoid missing any MSI interrupts:
SR 2.0, 1.1, 1.0
TDA2x: 2.0, 1.1, 1.0
DRA75x, DRA74x: 2.0, 1.1, 1.0
AM572x: 2.0, 1.1