SPRZ398K November 2012 – September 2024 DRA745 , DRA746 , DRA750 , DRA756
IO Glitches Can Occur When Changing IO Settings
Medium
Glitches up to multiple nano-seconds in length can occur on a Device IO when changing the IO setting via either of the below methods:
To workaround this issue, the Device LVCMOS IOs should be placed into Isolation mode when changing the IO settings as described above. Refer to the Device TRM section "Isolation Requirements" for more details.
SR 2.0, 1.1, 1.0
TDA2x: 2.0, 1.1, 1.0
DRA75x, DRA74x: 2.0, 1.1, 1.0
AM572x: 2.0, 1.1