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This document describes the known exceptions to the functional specifications (advisories) for the AM437x Sitara Cortex®-A9 Processors. See AM437x Sitara Processors.
This document also contains usage notes. Usage notes describe situations where the device's behavior may not match presumed or documented behavior. This may include behaviors that affect device performance or functional correctness.
For additional information, see the latest version of the AM437x Sitara Processors Technical Reference Manual.
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all processors and support tools. Each device has one of three prefixes: X, P, or null (no prefix) (for example, XAM4376ZDN). Texas Instruments recommends two of three possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (TMDX) through fully qualified production devices and tools (TMDS).
Device development evolutionary flow:
Support tool development evolutionary flow:
X and P devices and TMDX development-support tools are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
Production devices and TMDS development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (X or P) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used.
The device revision can be determined by the symbols marked on the top of the package. Figure 1-1 provides an example of the device markings.
NOTES:
Silicon revision is identified by a code marked on the package. The code is of the format AM4376x, where "x" denotes the silicon revision. Table 1-1 lists the information associated with each silicon revision for each device type. For more details on device nomenclature, see the device-specific data manual.
DEVICE REVISION CODE | SILICON REVISION | COMMENTS |
---|---|---|
A | 1.1 | Silicon revision PG1.1 |
B | 1.2 | Silicon revision PG1.2 |
Each silicon revision uses a specific revision of TI's ARM® Cortex®-A9 processor. The ARM Cortex-A9 processor variant and revision can be read from the Main ID Register. The DEVREV field (bits 31-28) of the Device_ID register located at address 0x44E10600 provides a 4-bit binary value that represents the device revision. The ROM code revision can be read from address 0x3BFFC on silicon revision 1.1 and 0x3FFFC on silicon revision 1.2. The ROM code version consists of two decimal numbers: major and minor. The major number is 0x27, and the minor number counts ROM code version. The ROM code version is coded as hexadecimal readable values; for example, ROM version 27.02 is coded as 0x2702. Table 1-2 shows the ARM Cortex-A9 Variant and Revision, Device Revision, and ROM Code Revision values for each silicon revision of the device.
SILICON REVISION | ARM CORTEX-A9 VARIANT AND REVISION | DEVICE REVISION | ROM REVISION | PL310 CACHE CONTROLLER VERSION |
---|---|---|---|---|
1.1 | r2p10 | 0001b | 27.01 | r3p2 |
1.2 | r2p10 | 0002b | 27.02 | r3p2 |
Advisories are numbered in the order in which they were added to this document. Some advisory numbers may be moved to the next revision and others may have been removed because the design exception was fixed or documented in the device-specific data manual or peripheral user's guide. When items are moved or deleted, the remaining numbers remain the same and are not re-sequenced.
NUMBER | TITLE | SILICON REVISION AFFECTED | |
---|---|---|---|
1.1 | 1.2 | ||
Section 3.1.1 | LPDDR2/DDR3: JEDEC Compliance for Minimum Self-Refresh Command Interval | X | X |
Section 3.1.2 | DDR3/DDR3L: JEDEC Specification Violation for DDR3 RESET Signal When Implementing RTC+DDR Mode | X | X |
NUMBER | TITLE | SILICON REVISION AFFECTED | |
---|---|---|---|
1.1 | 1.2 | ||
Advisory 1 | UART: Extra Assertion of FIFO Transmit DMA Request, UARTi_DMA_TX | X | X |
Advisory 2 | ROM: USB Host Boot is Unsupported | X | |
Advisory 3 | ROM: USB Client Boot is Unsupported | X | |
Advisory 4 | ROM: RGMII Clocking Register is Not Configured Properly at OPP50 | X | |
Advisory 5 | ROM: Trace Vector Does Not Reflect that TFTP Transfer Has Been Initiated | X | |
Advisory 6 | ROM: Booting from Redundant Image in NAND Does Not Work as Expected | X | |
Advisory 7 | ROM: NAND Booting is Slower than Expected | X | |
Advisory 8 | ROM: In NOR Low Latency Boot Mode, Wait Monitoring Will Not Work | X | |
Advisory 9 | ROM: NAND ECC May Not Be Chosen Correctly by the ROM | X | |
Advisory 10 | ROM: Peripheral Boot is Not Supported | X | |
Advisory 11 | Asynchronous Bridge Corruption | X | X |
Advisory 12 | DebugSS: Register Identifier Field (MasterID) of Statistics Collector Has a Default Value of 0x0 Instead of the Expected ID | X | X |
Advisory 13 | DSS: DSS Smart Standby May Cause Synchronization Issues | X | X |
Advisory 14 | DSS: DSS Limitations | X | X |
Advisory 15 | ROM: NAND Boot Mode is Unsupported | X | |
Advisory 16 | McASP: McASP to EDMA Synchronization Level Event Can Be Lost | X | X |
Advisory 17 | DebugSS: DebugSS Does Not Acknowledge Idle Request | X | X |
Advisory 19 | TSC_ADC: False Pen-up Interrupts | X | X |
Advisory 20 | GPTimer: Delay Needed to Read Some GPTimer Registers After Wakeup | X | X |
Advisory 21 | UART: UART0-5 Do Not Acknowledge Idle Request After DMA Has Been Enabled | X | X |
Advisory 22 | Watchdog Timers: Delay Needed to Read Some WDTimer Registers After Wakeup | X | X |
Advisory 24 | VDD_MPU_MON Not Connected to Die | X | X |
Advisory 25 | Ethernet Boot: ROM May Select 1-Gbit, Half-Duplex Mode During Auto-negotiation and Fail to Boot | X | X |
Advisory 26 | AutoCMD12 Mode: CMD12 Command is Not Issued on Write Transfer Completion | X | X |
Advisory 27 | UART: Spurious UART Interrupts When Using EDMA | X | X |
Advisory 28 | UART: Transactions to MDR1 Register May Cause Undesired Effect on UART Operation | X | X |
i2223 | ROM: Non-muxed Fast NOR boot does not onfigure A26 and A27 | X | X |
i2224 | DCAN: RAMINIT_DONE intermittently fails to latch completion | X | X |
i912 | QSPI: QSPI register bitfield incorrectly masked when read | X | X |
i2225 | Possible underflow condition when using EDMA with UART1, UART2, and UART3 | X | X |
i2226 | PRU-ICSS: Burst data transfer between ICSS instances not supported | X | X |