SPRZ422K August   2014  – May 2024 TMS320F28374S , TMS320F28375S , TMS320F28375S-Q1 , TMS320F28376S , TMS320F28377S , TMS320F28377S-Q1 , TMS320F28378S , TMS320F28379S

 

  1.   1
  2.   Abstract
  3. 1Usage Notes and Advisories Matrices
    1. 1.1 Usage Notes Matrix
    2. 1.2 Advisories Matrix
  4. 2Nomenclature, Package Symbolization, and Revision Identification
    1. 2.1 Device and Development Support Tool Nomenclature
    2. 2.2 Devices Supported
    3. 2.3 Package Symbolization and Revision Identification
  5. 3Silicon Revision C Usage Notes and Advisories
    1. 3.1 Silicon Revision C Usage Notes
      1. 3.1.1 PIE: Spurious Nested Interrupt After Back-to-Back PIEACK Write and Manual CPU Interrupt Mask Clear
      2. 3.1.2 Caution While Using Nested Interrupts
      3. 3.1.3 SYS/BIOS: Version Implemented in Device ROM is not Maintained
      4. 3.1.4 SDFM: Use Caution While Using SDFM Under Noisy Conditions
      5. 3.1.5 McBSP: XRDY Bit can Hold the Not-Ready Status (0) if New Data is Written to the DX1 Register Without Verifying if the XRDY Bit is in its Ready State (1)
    2. 3.2 Silicon Revision C Advisories
      1.      Advisory
      2.      Advisory
      3.      Advisory
      4.      Advisory
      5.      Advisory
      6.      Advisory
      7.      Advisory
      8.      Advisory
      9.      Advisory
      10.      Advisory
      11.      Advisory
      12.      Advisory
      13.      Advisory
      14.      Advisory
      15.      Advisory
      16.      Advisory
      17.      Advisory
      18.      Advisory
      19.      Advisory
      20.      Advisory
      21.      Advisory
      22.      Advisory
      23.      Advisory
      24.      Advisory
      25.      Advisory
      26.      Advisory
      27.      Advisory
      28.      Advisory
      29.      Advisory
      30.      Advisory
      31.      Advisory
      32.      Advisory
      33.      Advisory
      34.      Advisory
      35.      Advisory
      36.      Advisory
      37.      Advisory
  6. 4Silicon Revision B Usage Notes and Advisories
    1. 4.1 Silicon Revision B Usage Notes
    2. 4.2 Silicon Revision B Advisories
      1.      Advisory
      2.      Advisory
      3.      Advisory
      4.      Advisory
      5.      Advisory
      6.      Advisory
      7.      Advisory
      8.      Advisory
      9.      Advisory
  7. 5Documentation Support
  8. 6Trademarks
  9. 7Revision History

Advisory

Analog Bandgap References

Revisions Affected

B, C

Details

The Analog Subsystem includes internal bandgap reference circuits that are shared by the embedded analog modules. Table 3-1 shows the bandgap usage by module.

 

Table 3-1 Bandgap Usage by Module
BANDGAP ADC BUFFERED DAC CMPSS
BGA ADCA DACA
DACB		 CMPSS1
CMPSS2
BGB ADCB DACC CMPSS3
CMPSS4
BGC ADCC CMPSS5
CMPSS6
BGD ADCD CMPSS7
CMPSS8

Each bandgap reference—BGA, BGB, BGC, or BGD—will power up when one or more of the dependent modules are enabled. An active bandgap reference will power down if all dependent modules are disabled.

For example, bandgap B (BGB) is powered down unless one or more of the following register bits are set:

  • AdcbRegs.ADCCTL1.bit.ADCPWDNZ
  • DaccRegs.DACOUTEN.bit.DACOUTEN
  • Cmpss3Regs.COMPCTL.bit.COMPDACE
  • Cmpss4Regs.COMPCTL.bit.COMPDACE

The CMPSS and GPDAC power-up time specification in the TMS320F2837xS Real-Time Microcontrollers data sheet previously did not account for the bandgap power-up time. This 10-µs value has been increased to 500 µs to account for the bandgap power-up time.

Workarounds

If your application was utilizing a power-up time of 10 µs for the CMPSS and GPDAC, you do not need to increase it to 500 µs if the respective ADC on that bandgap was turned on before the CMPSS and GPDAC, and the ADC power-up time of 500 µs was adhered to.

For simplicity, it is recommended that 500 µs be used as the power-up time for both CMPSS and GPDAC.