SPRZ429N July 2014 – July 2024 AM5726 , AM5728 , AM5729
Refresh Rate Issue after Warm Reset
Medium
The refresh rate is programmed in the EMIF_SDRAM_REFRESH_CONTROL[15:0] REFRESH_RATE parameter and is calculated based off of the frequency of the DDR clock during normal operation.
When a warm reset is applied to the system, the DDR clock source is set to PLL bypass frequency which is much lower than the functional frequency of operation. Due to this frequency change, upon warm reset de-assertion the refresh rate will be too low until the DDR PLL is set to the functional frequency. This could result in unexpected behavior on the memory side.
There are 2 possible work-arounds:
SR 2.0, 1.1
TDA2x: 2.0, 1.1, 1.0
DRA75x, DRA74x: 2.0, 1.1, 1.0
AM572x: 2.0, 1.1