CRITICALITY

Medium

DESCRIPTION

In many end systems, the SoC's VOUT or DISPC_* parallel video output interface is used to connect to a TI FPDLink LVDS Serializer component (on the system board) such as the DS90UH925, which connects via FPDLink cable to a remote deserializer such as the DS90UH926 device which is typically used to drive a display.

In this scenario, the SoC's internal PLL is used to create the Video output clock that is used by the FPDLink Serializer internal PLL to create the higher frequency LVDS link clock. Depending on the jitter characteristics of the SoC's output clock, a high amount of jitter can be introduced into the serializer output. This can cause the remote LVDS de-serializer's PLL to become unlocked, resulting in a blank image.

A given target frequency for the SoC Video output clock can be achieved with different values of Multiplier M and Divider N (M/N). In general, lower values of M/N result in jitter characteristics that can cause the unlocked condition to occur.

GUIDELINES

The SoC PLL M/N values should be set with the highest valid values of M/N to achieve the desired frequency setting. This results in optimal jitter characteristics relative to the FPDLink device requirements.

For example, using a SoC PLL input clock of 20 MHz, a Video clock target frequency of 74.25 MHz can be achieved using either Option A (N=7, M=297, M4=19) or Option B (N=119, M=1782, M4=7). Option B is recommended.

REVISIONS IMPACTED

SR 2.0, 1.1

TDA2x: 2.0, 1.1, 1.0

DRA75x, DRA74x: 2.0, 1.1, 1.0

AM572x: 2.0, 1.1