SPRZ429N July 2014 – July 2024 AM5726 , AM5728 , AM5729
DPLL Controller Can Get Stuck While Transitioning to a Power Saving State
Low
NOTE: The previous title for this advisory was "DPLL Controller Sticks When Left Clock Requests Are Removed"
The DPLL Controller can get stuck if it is in transition to a low power state while its M/N ratio is being programmed.
Before re-programming the M/N ratio, SW has to ensure the DPLL cannot start an idle state transition. SW can disable DPLL idling by setting the DPLL AUTO_DPLL_MODE=0 or keeping a clock request active by setting a dependent clock domain in SW_WKUP.
SR 2.0, 1.1
TDA2x: 2.0, 1.1, 1.0
DRA75x, DRA74x: 2.0, 1.1, 1.0
AM572x: 2.0, 1.1