SPRZ429N July 2014 – July 2024 AM5726 , AM5728 , AM5729
Optional VOUT3 Clock Muxing Not Meeting IO Timing
Low
The optional vout3_clk function on the vin1a_fld0 pin (muxmode = 0x4) does not meet Device Data Manual timings for vout3 interface. Violation could be on order of approximately 2.5ns.
Use a software patch, contact your TI representative, to configure registers within Vayu which can modify the vout3_clk IO timing sufficiently to meet the Device Data Manual timings.
SR 1.0
TDA2x: 1.0
DRA75x, DRA74x: 1.0
AM572x: 1.0