SPRZ452I july   2018  – may 2023 AM6526 , AM6528 , AM6546 , AM6548

 

  1. 1Usage Notes and Advisories Matrices
  2. 2Nomenclature, Package Symbolization, and Revision Identification
    1. 2.1 Device and Development-Support Tool Nomenclature
    2. 2.2 Devices Supported
    3. 2.3 Package Symbolization and Revision Identification
  3. 3Silicon Revision 2.1, 2.0, 1.0 Usage Notes and Advisories
    1. 3.1 Silicon Revision 2.1, 2.0, 1.0 Usage Notes
      1. 3.1.1 Fail-Safe IO's: Latch-up Risk on Fail-Safe IOs
      2. 3.1.2 ADC: High Input Leakage Current May Impact ADC Accuracy
      3. 3.1.3 INTRTR: Spurious Interrupts Generated when Programming Certain Interrupt Routers
      4.      i2351
    2. 3.2 Silicon Revision 2.1, 2.0, 1.0 Advisories
      1. 3.2.1 Silicon Revision 2.1, 2.0, 1.0 Advisory List
      2.      i939
      3.      i2000
      4.      i2004
      5.      i2006
      6.      i2009
      7.      i2013
      8.      i2015
      9.      i2018
      10.      i2019
      11.      i2020
      12.      i2021
      13.      i2022
      14.      i2023
      15.      i2024
      16.      i2025
      17.      i2026
      18.      i2027
      19.      i2028
      20.      i2030
      21.      i2032
      22.      i2037
      23.      i2038
      24.      i2039
      25.      i2046
      26.      i2053
      27.      i2054
      28.      i2055
      29.      i2068
      30.      i2069
      31.      i2073
      32.      i2075
      33.      i2076
      34.      i2083
      35.      i2084
      36.      i2095
      37.      i2096
      38.      i2097
      39.      i2098
      40.      i2099
      41.      i2101
      42.      i2103
      43.      i2104
      44.      i2106
      45.      i2115
      46.      i2116
      47.      i2118
      48.      i2119
      49.      i2129
      50.      i2132
      51.      i2137
      52.      i2138
      53.      i2139
      54.      i2141
      55.      i2143
      56.      i2146
      57.      i2148
      58.      i2149
      59.      i2161
      60.      i2162
      61.      i2164
      62.      i2165
      63.      i2177
      64.      i2184
      65.      i2185
      66.      i2187
      67.      i2189
      68.      i2193
      69.      i2196
      70.      i2198
      71.      i2204
      72.      i2207
      73.      i2231
      74.      i2234
      75.      i2245
      76.      i2307
      77.      i2014
      78.      i2145
      79.      i2163
      80.      i2173
      81.      i2249
      82.      i2278
      83.      i2279
      84.      i2307
      85.      i2310
      86.      i2311
      87.      i2320
      88.      i2328
      89.      i2329
      90.      i2040
      91.      i2041
      92.      i2043
      93. 3.2.2 i2151
      94.      i2262
      95.      i2264
      96.      i2265
      97.      i2266
      98.      i2268
      99.      i2312
      100.      i2371
        1.       Trademarks
          1.        Revision History

i2099


Cortex-R5F: Deadlock Might Occur When One or More MPU Regions is Configured for Write Allocate Mode

Details:

There are two conditions where R5F can deadlock:

  • When software is performing series of store operations to cacheable write back/write allocate memory region and later on software execute barrier operation (DSB or DMB). R5F may hang at the barrier instruction.
  • When software is performing a mix of load and store operations within a tight loop and store operations are all writing to cacheable write back/write allocates memory regions, R5F may hang at one of the load instruction.

Workaround(s):

Disabling linefill optimization inside Cortex-R5F will eliminate deadlock condition.

To disable the linefill optimization, the software needs to set bit 13 (DLFO) of Auxiliary Control Register (See Cortex-R5F Technical Reference Manual for how to update Auxiliary Control Register).