SPRZ452I july 2018 – may 2023 AM6526 , AM6528 , AM6546 , AM6548
PRU_ICSSG: 100Mbit/s MII is not supported when the PRU_ICSSG is operating at frequencies < 250MHz
100Mbit/s MII is not supported when ICSSG_TXCFG0/1[12] TX_IPG_WIRE_CLK_EN = 0 and the PRU_ICSSG CORE functional clock is operating at frequencies < 250MHz.
For [M4_SR1.0], there is no workaround.
For [M4_SR2.0 and all other KS3 devices], the workaround to set ICSSG_TXCFG0/1[12] TX_IPG_WIRE_CLK_EN = 1 and program the minimum inter packet gap (ICSSG_TX_IPG0/1[15:0] TX_IPG0/1) as described in the device TRM. With this configuration and ICSSG_TXCFG0/1 [30:28] TX_CLK_DELAY0/1 set to the value defined in the device datasheet, 100Mbit/s MII support is not limited by the PRU_ICSSG CORE functional clock frequency.