SPRZ452I july   2018  – may 2023 AM6526 , AM6528 , AM6546 , AM6548

 

  1. 1Usage Notes and Advisories Matrices
  2. 2Nomenclature, Package Symbolization, and Revision Identification
    1. 2.1 Device and Development-Support Tool Nomenclature
    2. 2.2 Devices Supported
    3. 2.3 Package Symbolization and Revision Identification
  3. 3Silicon Revision 2.1, 2.0, 1.0 Usage Notes and Advisories
    1. 3.1 Silicon Revision 2.1, 2.0, 1.0 Usage Notes
      1. 3.1.1 Fail-Safe IO's: Latch-up Risk on Fail-Safe IOs
      2. 3.1.2 ADC: High Input Leakage Current May Impact ADC Accuracy
      3. 3.1.3 INTRTR: Spurious Interrupts Generated when Programming Certain Interrupt Routers
      4.      i2351
    2. 3.2 Silicon Revision 2.1, 2.0, 1.0 Advisories
      1. 3.2.1 Silicon Revision 2.1, 2.0, 1.0 Advisory List
      2.      i939
      3.      i2000
      4.      i2004
      5.      i2006
      6.      i2009
      7.      i2013
      8.      i2015
      9.      i2018
      10.      i2019
      11.      i2020
      12.      i2021
      13.      i2022
      14.      i2023
      15.      i2024
      16.      i2025
      17.      i2026
      18.      i2027
      19.      i2028
      20.      i2030
      21.      i2032
      22.      i2037
      23.      i2038
      24.      i2039
      25.      i2046
      26.      i2053
      27.      i2054
      28.      i2055
      29.      i2068
      30.      i2069
      31.      i2073
      32.      i2075
      33.      i2076
      34.      i2083
      35.      i2084
      36.      i2095
      37.      i2096
      38.      i2097
      39.      i2098
      40.      i2099
      41.      i2101
      42.      i2103
      43.      i2104
      44.      i2106
      45.      i2115
      46.      i2116
      47.      i2118
      48.      i2119
      49.      i2129
      50.      i2132
      51.      i2137
      52.      i2138
      53.      i2139
      54.      i2141
      55.      i2143
      56.      i2146
      57.      i2148
      58.      i2149
      59.      i2161
      60.      i2162
      61.      i2164
      62.      i2165
      63.      i2177
      64.      i2184
      65.      i2185
      66.      i2187
      67.      i2189
      68.      i2193
      69.      i2196
      70.      i2198
      71.      i2204
      72.      i2207
      73.      i2231
      74.      i2234
      75.      i2245
      76.      i2307
      77.      i2014
      78.      i2145
      79.      i2163
      80.      i2173
      81.      i2249
      82.      i2278
      83.      i2279
      84.      i2307
      85.      i2310
      86.      i2311
      87.      i2320
      88.      i2328
      89.      i2329
      90.      i2040
      91.      i2041
      92.      i2043
      93. 3.2.2 i2151
      94.      i2262
      95.      i2264
      96.      i2265
      97.      i2266
      98.      i2268
      99.      i2312
      100.      i2371
        1.       Trademarks
          1.        Revision History

i2265

DDR: Issuing MRR/MRW commands in self-refresh state (LPDDR4 only)

Details:

PWRCTL.stay_in_selfref=1'b1 allows user to pause in self-refresh 1 or self-refresh 2 states for software to perform Mode Register Read (MRR) and Mode Register Write (MRW) commands. If controller-PHY hardware handshake occurs while in Self Refresh Power Down (SRPD), then PWRCTL.stay_in_selfref=1 will not pause in self-refresh states as expected. The MRR/MRW commands could be sent in normal mode. Depending on if the MRR/MRW commands being sent needs the DRAM to be in Self Refresh, this may violate JEDEC requirements for LPDDR4.

Workaround(s):

Use the following sequence to issue software initiated MRR/MRW commands during entering self-refresh:

1. Disable PHY master interface

  • Set DFIPHYMSTR.dfi_phymstr_en to 0 (note that this is documented as static, but implemented as dynamic register)

2. Disable the following automatic self-refresh entry (if using)

  • Set PWRCTL.selfref_en to 0

3. Ensure that DDR is not in self-refresh or SR-Powerdown.

  • Wait for STAT.operating_mode to be not equal to 3'b011 (Self-Refresh/SR-Powerdown mode)

4. Enter self-refresh 1 state

  • Set PWRCTL.stay_in_selfref to 1
  • Set PWRCTL.selfref_sw to 1
  • Wait for STAT.selfref_type to be not equal to 2'b01 (Self-Refresh caused by PHY master request)
  • If STAT.selfref_state is 2'b10 (SR-Powerdown) or 2'b11(Self-Refresh 2), set PWRCTL.stay_in_selfref to 0 and PWRCTL.selfref_sw to 0, then go back to step 2
  • Wait for STAT.selfref_state to become 2'b01 (Self-Refresh 1)

5. Send MRR/MRW commands using MRCTRL0 and MRCTRL1 registers

6. Enter SR-Powerdown mode.

  • Set PWRCTL.stay_in_selfref to 0
  • Wait for STAT.selfref_state to become 2'b10 (SR-Powerdown)

7. Exit self-refresh 2 state

  • Set PWRCTL.stay_in_selfref to 1
  • Set PWRCTL.selfref_sw to 0
  • Wait for STAT.selfref_state to become 2'b11 (Self-Refresh 2)

8. Send MRR/MRW commands using MRCTRL0 and MRCTRL1 registers

9. Exit self-refresh mode

  • Set PWRCTL.selfref_sw to 0
  • Wait for STAT.selfref_state to become 2'b00 (Not Self-Refresh)

10. Enable PHY master interface

  • Set DFIPHYMSTR.dfi_phymstr_en to 1