SPRZ452I july 2018 – may 2023 AM6526 , AM6528 , AM6546 , AM6548
MSMC: SW considerations for HW data coherency due to inconsistent views of memory
Hardware-Based Cache coherency and IO coherency is supported for both On-Chip Shared SRAM and DDR in the Keystone 3 Platform. To maintain proper data coherency, all data requestors are required to maintain a common consistent view of memory for all transactions to the same memory location (ie. memory type and shareability). A mismatch of these memory attributes can result in a loss of data coherency.
In the absence of a common, consistent view of memory for all accesses to memory, software is required to use cache maintenance operations, barrier operations, and IPC messages to maintain data coherency. Caching requestors are required to use clean and invalidate cache maintenance operations before and after each memory access in order to move data from local caches back out to main memory. Barrier operations are needed to ensure all memory write accesses have reached main memory and therefore observable to all requestors. Messages to other requestors are required to signal when these operations have completed. The memory granularity for Shared SRAM and DDR is 64B. Overlapping accesses from different processing entities to a memory location should be avoided to prevent potential race conditions. Software is required to manage data ownership and manually push data out back to main memory prior to transferring data ownership and/or enabling data observability by all memory requestors in the system.