Details:

PCIe fails to link up if SERDES lanes not used by PCIe are assigned to another protocol. For example, link training fails if lanes 2 and 3 are assigned to another protocol while lanes 0 and 1 are used for PCIe to form a two lane link. This failure is due to an incorrect tie-off on an internal status signal indicating electrical idle.

Status signals going from SERDES to PCIe Controller are tied-off when a lane is not assigned to PCIe. Signal indicating electrical idle is incorrectly tied-off to a state that indicates non-idle. As a result, PCIe sees unused lanes to be out of electrical idle and this causes LTSSM to exit Detect.Quiet state without waiting for 12ms timeout to occur. If a receiver is not detected on the first receiver detection attempt in Detect.Active state, LTSSM goes back to Detect.Quiet and again moves forward to Detect.Active state without waiting for 12ms as required by PCIe base specification. Since wait time in Detect.Quiet is skipped, multiple receiver detect operations are performed back-to-back without allowing time for capacitances on the transmit lines to discharge. This causes subsequent receiver detections to always fail even if a receiver gets connected eventually.

Workaround(s):

One of the following two workarounds can be applied when unused lane of SERDES is assigned to a different protocol.

1. Important to note that this workaround only works for 1-lane PCIe configuration. This workaround involves enabling receiver detect override by setting TX_RCVDET_OVRD_PREG_j register of the lane running PCIe to 0x2. This causes SERDES to indicate successful receiver detect when LTSSM is in Detect.Active state, whether a receiver is actually present or not. If the receiver is present, LTSSM proceeds to link up as expected. However if receiver is not present, LTSSM will time out in Polling.Configuration substate since the expected training sequence packets will not be received.

2. This workaround involves the following sequence. These steps have to be following for initial link up and for any subsequent link up if link goes down at any point of operation.

Step1: Enable and disable link training in quick succession using LINK_TRAINING_ENABLE field in PCIE_USER_CMD_STATUS register. Ensure that the two register writes for this are occurring in order. Link training has to be enabled at least for one clock cycle.

Step2: Wait for approximately 20ms. This does not have to be accurate. Minimum wait time has to be close to 5ms.

Step3: Check LTSSM_STATE field in PCIE_USER_LINKSTATUS register for current LTSSM state. If state is Detect.Quiet, then repeat from step 1. If state is not Detect.Quiet, exit workaround sequence as receiver was detected and link training has progressed as expected.