SPRZ455D december 2020 – june 2023 DRA829J , DRA829J-Q1 , DRA829V , DRA829V-Q1 , TDA4VM , TDA4VM-Q1
ADVANCE INFORMATION
DDR: Dual-rank non-power-of-2 density not supported with row-cs-bank-col address mapping
DDR controller does not support dual-rank non-power-of-2 density LPDDR4 devices with row-cs-bank-col address mapping.
Please note that the above does not apply to single-rank non-power-of-2 density devices as well as all power-of-2 density devices.
Use cs-row-bank-col address mapping with dual-rank non-power-of-2 density LPDDR4 devices. To ensure cs-row-bank-col address mapping is selected, the cs_lower_addr_en field in the Cadence controller register must be set to 0.