SPRZ455D december   2020  – june 2023 DRA829J , DRA829J-Q1 , DRA829V , DRA829V-Q1 , TDA4VM , TDA4VM-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1Modules Affected
  3. 2Nomenclature, Package Symbolization, and Revision Identification
    1. 2.1 Device and Development-Support Tool Nomenclature
    2. 2.2 Devices Supported
    3. 2.3 Package Symbolization and Revision Identification
  4. 3Silicon Revision 1.1/1.0 Usage Notes and Advisories
    1. 3.1 Silicon Revision 1.1/1.0 Usage Notes
      1.      i2134
    2. 3.2 Silicon Revision 1.1/1.0 Advisories
    3.     i2024
    4.     i2038
    5.     i2048
    6.     i2049
    7.     i2050
    8.     i2052
    9.     i2053
    10.     i2054
    11.     i2055
    12.     i2062
    13.     i2063
    14.     i2064
    15.     i2065
    16.     i2067
    17.     i2079
    18.     i2081
    19.     i2083
    20.     i2085
    21.     i2086
    22.     i2087
    23.     i2090
    24.     i2091
    25.     i2092
    26.     i2093
    27.     i2094
    28.     i2095
    29.     i2096
    30.     i2097
    31.     i2098
    32.     i2099
    33.     i2100
    34.     i2101
    35.     i2102
    36.     i2103
    37.     i2103
    38.     i2115
    39.     i2116
    40.     i2117
    41.     i2118
    42.     i2119
    43.     i2120
    44.     i2121
    45.     i2122
    46.     i2123
    47. 3.3 i2124
    48. 3.4 i2126
    49. 3.5 i2127
    50.     i2128
    51.     i2129
    52.     i2131
    53.     i2132
    54.     i2133
    55.     i2134
    56.     i2137
    57.     i2138
    58.     i2139
    59.     i2141
    60.     i2143
    61.     i2144
    62.     i2145
    63.     i2146
    64.     i2147
    65.     i2148
    66.     i2149
    67. 3.6 i2150
    68. 3.7 i2151
    69. 3.8 i2152
    70.     i2153
    71.     i2154
    72.     i2155
    73.     i2157
    74.     i2159
    75.     i2160
    76.     i2161
    77.     i2162
    78.     i2163
    79.     i2164
    80.     i2166
    81.     i2168
    82.     i2171
    83.     i2173
    84.     i2174
    85.     i2177
    86.     i2178
    87.     i2179
    88.     i2180
    89.     i2182
    90.     i2183
    91.     i2184
    92.     i2185
    93.     i2187
    94.     i2188
    95.     i2189
    96.     i2190
    97.     i2191
    98.     i2196
    99.     i2197
    100.     i2198
    101.     i2199
    102.     i2200
    103.     i2205
    104.     i2207
    105.     i2208
    106.     i2210
    107.     i2211
    108.     i2213
    109.     i2214
    110.     i2215
    111.     i2216
    112.     i2217
    113.     i2219
    114.     i2221
    115.     i2227
    116.     i2228
    117.     i2229
    118.     i2230
    119.     i2232
    120.     i2234
    121.     i2235
    122.     i2238
    123.     i2239
    124.     i2244
    125.     i2245
    126.     i2246
    127.     i2249
    128.     i2253
    129.     i2257
    130.     i2271
    131.     i2274
    132.     i2275
    133.     i2277
    134.     i2278
    135.     i2279
    136.     i2283
    137.     i2305
    138.     i2306
    139.     i2307
    140.     i2310
    141.     i2311
    142.     i2312
    143.     i2320
    144.     i2329
    145.     i2351
    146.     i2362
    147.     i2366
    148.     i2371
    149.     i2383
  5.   Trademarks
  6.   Revision History

i2099


R5FSS: Deadlock Might Occur When One or More MPU Regions are Configured for Write Allocate Mode

Details:

There are two conditions where R5FSS can deadlock:

  • When software is performing series of store operations to cacheable write back/write allocate memory region and later on software execute barrier operation (DSB or DMB). R5FSS may hang at the barrier instruction.
  • When software is performing a mix of load and store operations within a tight loop and store operations are all writing to cacheable write back/write allocates memory regions, R5FSS may hang at one of the load instruction.

Workaround(s):

Disabling linefill optimization inside R5FSS will eliminate deadlock condition.

To disable the linefill optimization, the software needs to set bit 13 (DLFO) of Auxiliary Control Register (See Cortex-R5F Technical Reference Manual for how to update Auxiliary Control Register).