SPRZ466C March   2020  – February 2024 TMS320F280021 , TMS320F280021-Q1 , TMS320F280023 , TMS320F280023-Q1 , TMS320F280023C , TMS320F280025 , TMS320F280025-Q1 , TMS320F280025C , TMS320F280025C-Q1

 

  1.   1
  2.   TMS320F28002x Real-Time MCUs Silicon ErrataSilicon Revisions A, 0
  3. 1Usage Notes and Advisories Matrices
    1. 1.1 Usage Notes Matrix
    2. 1.2 Advisories Matrix
  4. 2Nomenclature, Package Symbolization, and Revision Identification
    1. 2.1 Device and Development-Support Tool Nomenclature
    2. 2.2 Devices Supported
    3. 2.3 Package Symbolization and Revision Identification
  5. 3Silicon Revision A Usage Notes and Advisories
    1. 3.1 Silicon Revision A Usage Notes
      1. 3.1.1 PIE: Spurious Nested Interrupt After Back-to-Back PIEACK Write and Manual CPU Interrupt Mask Clear
      2. 3.1.2 Caution While Using Nested Interrupts
      3. 3.1.3 Security: The primary layer of defense is securing the boundary of the chip, which begins with enabling JTAGLOCK and Zero-pin Boot to Flash feature
    2. 3.2 Silicon Revision A Advisories
      1.      Advisory
      2.      Advisory
      3. 3.2.1 Advisory
      4.      Advisory
      5.      Advisory
      6.      Advisory
      7. 3.2.2 Advisory
      8.      Advisory
      9.      Advisory
      10.      Advisory
      11. 3.2.3 Advisory
      12.      Advisory
      13. 3.2.4 Advisory
      14.      Advisory
      15. 3.2.5 Advisory
      16. 3.2.6 Advisory
  6. 4Silicon Revision 0 Usage Notes and Advisories
    1. 4.1 Silicon Revision 0 Usage Notes
    2. 4.2 Silicon Revision 0 Advisories
      1.      Advisory
  7. 5Documentation Support
  8. 6Trademarks
  9. 7Revision History

1.2 Advisories Matrix

Table 1-2 Advisories Matrix
MODULE DESCRIPTION SILICON REVISIONS AFFECTED
0 A
ADC ADC: Interrupts may Stop if INTxCONT (Continue-to-Interrupt Mode) is not Set Yes Yes
ADC ADC: DMA Read of Stale Result Yes Yes
Boot ROM, MPOST Boot-ROM, MPOST: Longer Boot Time With MPOST Enabled Yes Yes
BOR BOR: VDDIO Between 2.45 V and 3.0 V can Result in Multiple XRSn Pulses Yes Yes
DCAN During DCAN FIFO Mode, Received Messages May be Placed Out of Order in the FIFO Buffer Yes Yes
ePWM ePWM: An ePWM Glitch can Occur if a Trip Remains Active at the End of the Blanking Window Yes Yes
ePWM ePWM: Event Latch (DCxEVTxLAT) of "DC Event-Based CBC Trip" May not Extend Trigger Pulse as Expected When Asynchronous Path is Selected Yes No
ePWM ePWM: Trip Events Will Not be Filtered by the Blanking Window for the First 3 Cycles After the Start of a Blanking Window Yes Yes
eQEP eQEP: Position Counter Incorrectly Reset on Direction Change During Index Yes Yes
FPU FPU: FPU-to-CPU Register Move Operation Preceded by Any FPU 2p Operation Yes Yes
I2C I2C: Target Transmitter Mode, Standard Mode SDA Timings Limitation Yes Yes
LIN LIN: Inconsistent Sync Field Error (ISFE) Flag/Interrupt Not Set When Sync Field is Erroneous Yes Yes
Memory Memory: Prefetching Beyond Valid Memory Yes Yes
SYSTEM SYSTEM: HIC Illegal Read Error Flag Does not Get Asserted in Pagesel=0 Mode Yes Yes
SYSTEM SYSTEM: Multiple Successive Writes to CLKSRCCTL1 Can Cause a System Hang Yes Yes
Diagnostics Avoiding Spurious Interrupts While Using HWBIST Yes Yes
PLL PLL Reference Clock Lost Detection: Missing Clock Flag may be Incorrectly Activated Yes Yes