SPRZ496D October   2021  – May 2024 TMS320F280033 , TMS320F280034 , TMS320F280034-Q1 , TMS320F280036-Q1 , TMS320F280036C-Q1 , TMS320F280037 , TMS320F280037-Q1 , TMS320F280037C , TMS320F280037C-Q1 , TMS320F280038-Q1 , TMS320F280038C-Q1 , TMS320F280039 , TMS320F280039-Q1 , TMS320F280039C , TMS320F280039C-Q1

 

  1.   1
  2.   TMS320F28003x Real-Time MCUs Silicon ErrataSilicon Revision 0
  3. 1Usage Notes and Advisories Matrices
    1. 1.1 Usage Notes Matrix
    2. 1.2 Advisories Matrix
  4. 2Nomenclature, Package Symbolization, and Revision Identification
    1. 2.1 Device and Development-Support Tool Nomenclature
    2. 2.2 Devices Supported
    3. 2.3 Package Symbolization and Revision Identification
  5. 3Silicon Revision 0 Usage Notes and Advisories
    1. 3.1 Silicon Revision 0 Usage Notes
      1. 3.1.1 PIE: Spurious Nested Interrupt After Back-to-Back PIEACK Write and Manual CPU Interrupt Mask Clear
      2. 3.1.2 Caution While Using Nested Interrupts
      3. 3.1.3 Security: The primary layer of defense is securing the boundary of the chip, which begins with enabling JTAGLOCK and Zero-pin Boot to Flash feature
    2. 3.2 Silicon Revision 0 Advisories
      1. 3.2.1  Advisory
      2.      Advisory
      3.      Advisory
      4. 3.2.2  Advisory
      5.      Advisory
      6.      Advisory
      7.      Advisory
      8.      Advisory
      9. 3.2.3  Advisory
      10.      Advisory
      11. 3.2.4  Advisory
      12.      Advisory
      13.      Advisory
      14.      Advisory
      15. 3.2.5  Advisory
      16.      Advisory
      17. 3.2.6  Advisory
      18. 3.2.7  Advisory
      19.      Advisory
      20. 3.2.8  Advisory
      21.      Advisory
      22. 3.2.9  Advisory
      23. 3.2.10 Advisory
      24.      Advisory
      25.      Advisory
      26.      Advisory
      27.      Advisory
  6. 4Documentation Support
  7. 5Trademarks
  8. 6Revision History

Advisory

ADC: DMA Read of Stale Result

Revision Affected

0

Details

The ADCINT flag can be set before the ADCRESULT value is latched (see the tLAT and tINT(LATE) columns in the ADC Timings table of the TMS320F28003x Real-Time Microcontrollers data sheet). The DMA can read the ADCRESULT value as soon as 3 cycles after the ADCINT trigger is set. As a result, the DMA could read a prior ADCRESULT value when the user expects the latest result if all of the following are true:

  • The ADC is in late interrupt mode.
  • The ADC operates in a mode where tINT(LATE) occurs 3 or more cycles before tLAT (ADCCTL2 [PRESCALE] > 2).
  • The DMA is triggered from the ADCINT signal.
  • The DMA immediately reads the ADCRESULT value associated with that ADCINT signal without reading any other values first.
  • The DMA was idle when it received the ADCINT trigger.

Only the DMA reads listed above could result in reads of stale data; the following non-DMA methods will always read the expected data:

  • The ADCINT flag triggers a CLA task.
  • The ADCINT flag triggers a CPU ISR.
  • The CPU polls the ADCINT flag.

Workaround

Trigger two DMA channels from the ADCINT flag. The first channel acts as a dummy transaction. This will result in enough delay that the second channel will always read the fresh ADC result.