Details:

The DDR PHY updates VREFca for the command/address bus during LPDDR4 Command Bus Training (CBT). Bit 3 in LPDDR4 Mode Register 13 (MR13) defines the VRef Current Generator (VRCG) mode inside the LPDDR4 device. If this bit is set to 0, the VREFca settling time is too long for subsequent operations to work properly. To ensure proper operation of CBT, bit 3 in MR13 must be set to 1 (VRef Fast Response high current mode) during CBT.

Workaround(s):

To ensure proper operation, VRef Fast Response high current mode should be enabled during both Command Bus Training (CBT) and Write DQ Vref Training. This can be done by setting the following fields to 1:

For chip select 0: PI_MR13_DATA_0[3] in the DDRSS_PI_259 register

For chip select 1: PI_MR13_DATA_1[3] in the DDRSS_PI_261 register

For chip select 2: PI_MR13_DATA_2[3] in the DDRSS_PI_263 register

For chip select 3: PI_MR13_DATA_3[3] in the DDRSS_PI_265 register