SPRZ544B March   2023  – December 2024 AM62A3 , AM62A3-Q1 , AM62A7 , AM62A7-Q1

 

  1.   1
  2. 1Usage Notes and Advisories Matrices
    1. 1.1 Devices Supported
  3. 2Silicon Usage Notes and Advisories
    1. 2.1 Silicon Usage Notes
      1.      i2351
      2.      i2372
      3.      i2424
    2. 2.2 Silicon Advisories
      1.      i2049
      2.      i2062
      3.      i2097
      4.      i2134
      5.      i2189
      6.      i2196
      7.      i2199
      8.      i2208
      9.      i2249
      10.      i2278
      11.      i2279
      12.      i2310
      13.      i2311
      14.      i2312
      15.      i2366
      16.      i2371
      17.      i2120
      18.      i2137
      19.      i2190
      20.      i2253
      21.      i2373
      22.      i2383
      23.      i2401
      24.      i2407
      25.      i2409
      26.      i2410
      27.      i2376
      28.      i2399
      29.      i2413
      30.      i2414
      31.      i2419
      32.      i2420
      33.      i2421
      34.      i2422
      35.      i2423
      36.      i2431
      37.      i2435
  4.   Trademarks
  5.   Revision History

i2424

PLL: PLL Programming Sequence May Introduce PLL Instability

Details:

PLL programming sequence has been changed to ensure that, if used, all calibration fields are configured prior to enabling the PLL calibration. In addition to the change to the control of the calibration logic, other changes are implemented so that PLL parameters are unchanged while the PLL is enabled.

When in integer mode, the software enables the PLL calibration feature on calibration-capable PLLs. The previous software adjusted calibration modes after CAL_LOCK was asserted. These writes have been observed to cause a loss of PLL lock on some devices. Additionally, even on susceptible devices, the loss of lock is intermittent, but when it occurs, dependent circuitry runs at an incorrect frequency; this wrong frequency can show up as slow algorithm execution or communication failures.

Limit on the impact: The calibration logic cannot be used when the PLL is in fractional mode. Therefore, PLLs that are programmed to use fractional mode should not see a failure related to the calibration programmation. Nevertheless, because of the change to the full PLL sequence, the new software is recommended for all users.

Workaround(s):

Do not use clk_pll_16fft_cal_option4() in SYSFW. Ensure to use updated PLL programming sequences in SDK v10.0 or later when performing any PLL configuration change.