SPRZ544B March   2023  – December 2024 AM62A3 , AM62A3-Q1 , AM62A7 , AM62A7-Q1

 

  1.   1
  2. 1Usage Notes and Advisories Matrices
    1. 1.1 Devices Supported
  3. 2Silicon Usage Notes and Advisories
    1. 2.1 Silicon Usage Notes
      1.      i2351
      2.      i2372
      3.      i2424
    2. 2.2 Silicon Advisories
      1.      i2049
      2.      i2062
      3.      i2097
      4.      i2134
      5.      i2189
      6.      i2196
      7.      i2199
      8.      i2208
      9.      i2249
      10.      i2278
      11.      i2279
      12.      i2310
      13.      i2311
      14.      i2312
      15.      i2366
      16.      i2371
      17.      i2120
      18.      i2137
      19.      i2190
      20.      i2253
      21.      i2373
      22.      i2383
      23.      i2401
      24.      i2407
      25.      i2409
      26.      i2410
      27.      i2376
      28.      i2399
      29.      i2413
      30.      i2414
      31.      i2419
      32.      i2420
      33.      i2421
      34.      i2422
      35.      i2423
      36.      i2431
      37.      i2435
  4.   Trademarks
  5.   Revision History

i2401

CPSW: Host Timestamps Cause CPSW Port to Lock up

Details:

The CPSW offers two mechanisms for communicating packet ingress timestamp information to the host.

The first mechanism is via the CPTS Event FIFO which records timestamps when triggered by certain events. One such event is the reception of an Ethernet packet with a specified EtherType field. Most commonly this is used to capture ingress timestamps for PTP packets. With this mechanism the host must read the timestamp (from the CPTS FIFO) separately from the packet payload which is delivered via DMA. This mode is supported and is not affected by this errata.

The second mechanism is to enable receive timestamps for all packets, not just PTP packets. With this mechanism the timestamp is delivered alongside the packet payload via DMA. This second mechanism is the subject of this errata.

When the CPTS host timestamp is enabled, every packet to the internal CPSW port FIFO requires a timestamp from the CPTS. When the packet preamble is corrupted due to EMI or any other corruption mechanism a timestamp request may not be sent to the CPTS. In this case the CPTS will not produce the timestamp which causes a lockup condition in the CPSW port FIFO. When the CPTS host timestamp is disabled by clearing the tstamp_en bit in the CPTS_CONTROL register the lockup condition is prevented from occurring.

Workaround(s):

Ethernet to host timestamps must be disabled.

CPTS Event FIFO timestamping can be used instead of CPTS host timestamps.