SPRZ580 December   2024 AM62D-Q1

 

  1.   1
  2. 1Usage Notes and Advisories Matrices
    1. 1.1 Devices Supported
  3. 2Silicon Usage Notes and Advisories
    1. 2.1 Silicon Usage Notes
      1.      i2351
      2.      i2372
    2. 2.2 Silicon Advisories
      1.      i2049
      2.      i2062
      3.      i2134
      4.      i2189
      5.      i2196
      6.      i2199
      7.      i2208
      8.      i2249
      9.      i2278
      10.      i2279
      11.      i2310
      12.      i2311
      13.      i2312
      14.      i2366
      15.      i2371
      16.      i2120
      17.      i2137
      18.      i2253
      19.      i2383
      20.      i2401
      21.      i2407
      22.      i2409
      23.      i2410
      24.      i2376
      25.      i2399
      26.      i2413
      27.      i2414
      28.      i2417
      29.      i2419
      30.      i2420
      31.      i2421
      32.      i2422
      33.      i2423
      34.      i2431
      35.      i2435
  4.   Trademarks
  5.   Revision History

i2417

Boot: GPMC NAND configured to slower clock speed

Details:

When using GPMC NAND boot mode the GPMCFCLKDIVIDER field of the GPMC_CONFIG1 register bit [1:0] (i.e. GPMCFCLKDIVIDER) gets set to 1 which causes a divide by 2 for the GPMC_FCLK.

The ROM uses very conservative CONFIG timing values anyways so end result may not really adversely affect throughput.

Workaround(s):

None.