SWCU191 February 2022 CC1311P3 , CC1311R3 , CC2651P3 , CC2651R3 , CC2651R3SIPA
In cache mode, the RAM block functions as an 8K 4-way random replacement cache for the FLASH block (see Figure 9-5). The GPRAM space is not available in cache mode.
In cache mode, all CPU accesses to the FLASH address space are directed to the cache first. The cache looks up the input address in the internal tag RAM to determine whether the access is a cache hit or a cache miss.
In the case of a cache miss, the access is forwarded to the FLASH block. The response from the FLASH block is routed back to the cache, then the cache is updated.
In the case of a cache hit, the data is fetched directly from the cache RAM.
The cache also contains a line buffer because the cache RAM word size is 64 bits. The objective of the line buffer is to prevent refetching the 32-bit part of the data that has already been fetched (but not used) in the previous access. The line buffer prevents both TAG and CACHE lookup if the data is already in the line buffer.
The cache line buffer is cleared as a part of the invalidation scheme.