SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7
#GPT_GPT_MAP1_TABLE_1 lists the memory-mapped registers for the GPT registers. All register offset addresses not listed in #GPT_GPT_MAP1_TABLE_1 should be considered as reserved locations and the register contents should not be modified.
| Offset | Acronym | Register Name | Section |
|---|---|---|---|
| 0h | CFG | Configuration | #GPT_GPT_MAP1_GPT_ALL_CFG |
| 4h | TAMR | Timer A Mode | #GPT_GPT_MAP1_GPT_ALL_TAMR |
| 8h | TBMR | Timer B Mode | #GPT_GPT_MAP1_GPT_ALL_TBMR |
| Ch | CTL | Control | #GPT_GPT_MAP1_GPT_ALL_CTL |
| 10h | SYNC | Synch Register | #GPT_GPT_MAP1_GPT_ALL_SYNC |
| 18h | IMR | Interrupt Mask | #GPT_GPT_MAP1_GPT_ALL_IMR |
| 1Ch | RIS | Raw Interrupt Status | #GPT_GPT_MAP1_GPT_ALL_RIS |
| 20h | MIS | Masked Interrupt Status | #GPT_GPT_MAP1_GPT_ALL_MIS |
| 24h | ICLR | Interrupt Clear | #GPT_GPT_MAP1_GPT_ALL_ICLR |
| 28h | TAILR | Timer A Interval Load Register | #GPT_GPT_MAP1_GPT_ALL_TAILR |
| 2Ch | TBILR | Timer B Interval Load Register | #GPT_GPT_MAP1_GPT_ALL_TBILR |
| 30h | TAMATCHR | Timer A Match Register | #GPT_GPT_MAP1_GPT_ALL_TAMATCHR |
| 34h | TBMATCHR | Timer B Match Register | #GPT_GPT_MAP1_GPT_ALL_TBMATCHR |
| 38h | TAPR | Timer A Pre-scale | #GPT_GPT_MAP1_GPT_ALL_TAPR |
| 3Ch | TBPR | Timer B Pre-scale | #GPT_GPT_MAP1_GPT_ALL_TBPR |
| 40h | TAPMR | Timer A Pre-scale Match | #GPT_GPT_MAP1_GPT_ALL_TAPMR |
| 44h | TBPMR | Timer B Pre-scale Match | #GPT_GPT_MAP1_GPT_ALL_TBPMR |
| 48h | TAR | Timer A Register | #GPT_GPT_MAP1_GPT_ALL_TAR |
| 4Ch | TBR | Timer B Register | #GPT_GPT_MAP1_GPT_ALL_TBR |
| 50h | TAV | Timer A Value | #GPT_GPT_MAP1_GPT_ALL_TAV |
| 54h | TBV | Timer B Value | #GPT_GPT_MAP1_GPT_ALL_TBV |
| 5Ch | TAPS | Timer A Pre-scale Snap-shot | #GPT_GPT_MAP1_GPT_ALL_TAPS |
| 60h | TBPS | Timer B Pre-scale Snap-shot | #GPT_GPT_MAP1_GPT_ALL_TBPS |
| 64h | TAPV | Timer A Pre-scale Value | #GPT_GPT_MAP1_GPT_ALL_TAPV |
| 68h | TBPV | Timer B Pre-scale Value | #GPT_GPT_MAP1_GPT_ALL_TBPV |
| 6Ch | DMAEV | DMA Event | #GPT_GPT_MAP1_GPT_ALL_DMAEV |
| FB0h | VERSION | Peripheral Version | #GPT_GPT_MAP1_GPT_ALL_VERSION |
| FB4h | ANDCCP | Combined CCP Output | #GPT_GPT_MAP1_GPT_ALL_ANDCCP |
Complex bit access types are encoded to fit into small table cells. #GPT_GPT_MAP1_LEGEND shows the codes that are used for access types in this section.
| Access Type | Code | Description |
|---|---|---|
| Read Type | ||
| R | R | Read |
| Write Type | ||
| W | W | Write |
| W1C | W 1C |
Write 1 to clear |
| Reset or Default Value | ||
| -n | Value after reset or the default value | |
CFG is shown in #GPT_GPT_MAP1_GPT_ALL_CFG_FIGURE and described in #GPT_GPT_MAP1_GPT_ALL_CFG_TABLE.
Return to the Summary Table.
Configuration
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | CFG | ||||||||||||||||||||||||||||||
| R-0h | R/W-0h | ||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-3 | RESERVED | R | 0h | Reserved |
| 2-0 | CFG | R/W | 0h | GPT Configuration 0x2- 0x3 - Reserved 0x5- 0x7 - Reserved 0h = 32BIT_TIMER : 32-bit timer configuration 4h = 16BIT_TIMER
: 16-bit timer configuration. |
TAMR is shown in #GPT_GPT_MAP1_GPT_ALL_TAMR_FIGURE and described in #GPT_GPT_MAP1_GPT_ALL_TAMR_TABLE.
Return to the Summary Table.
Timer A Mode
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| TCACT | TACINTD | TAPLO | TAMRSU | TAPWMIE | TAILD | ||
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| TASNAPS | TAWOT | TAMIE | TACDIR | TAAMS | TACM | TAMR | |
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-16 | RESERVED | R | 0h | Reserved |
| 15-13 | TCACT | R/W | 0h | Timer Compare Action Select 0h = DIS_CMP : Disable compare operations 1h = Toggle State on Time-Out 2h = Clear CCP output pin on Time-Out 3h = Set CCP output pin on Time-Out 4h = Set CCP output pin immediately and toggle on Time-Out 5h = Clear CCP output pin immediately and toggle on Time-Out 6h = Set CCP output pin immediately and clear on Time-Out 7h = Clear CCP output pin immediately and set on Time-Out |
| 12 | TACINTD | R/W | 0h | One-Shot/Periodic Interrupt Disable 0h = Time-out interrupt function as normal 1h = Time-out interrupt are disabled |
| 11 | TAPLO | R/W | 0h | GPTM Timer A PWM Legacy Operation 0 Legacy operation with CCP pin driven Low when the TAILR register is reloaded after the timer reaches 0. 1 CCP is driven High when the TAILR register is reloaded after the timer reaches 0. This bit is only valid in PWM mode. 0h = Legacy operation 1h = CCP output pin is set to 1 on time-out |
| 10 | TAMRSU | R/W | 0h | Timer A Match Register Update mode This bit defines when the TAMATCHR and TAPR registers are updated. If the timer is disabled (CTL.TAEN = 0) when this bit is set, TAMATCHR and TAPR are updated when the timer is enabled. If the timer is stalled (CTL.TASTALL = 1) when this bit is set, TAMATCHR and TAPR are updated according to the configuration of this bit. 0h = Update TAMATCHR and TAPR, if used, on the next cycle. 1h = Update TAMATCHR and TAPR, if used, on the next time-out. |
| 9 | TAPWMIE | R/W | 0h | GPTM Timer A PWM Interrupt Enable This bit enables interrupts in PWM mode on rising, falling, or both edges of the CCP output, as defined by the CTL.TAEVENT In addition, when this bit is set and a capture event occurs, Timer A automatically generates triggers to the DMA if the trigger capability is enabled by setting the CTL.TAOTE bit and the DMAEV.CAEDMAEN bit respectively. 0 Capture event interrupt is disabled. 1 Capture event interrupt is enabled. This bit is only valid in PWM mode. 0h = Interrupt is disabled. 1h = Interrupt is enabled. This bit is only valid in PWM mode. |
| 8 | TAILD | R/W | 0h | GPT Timer A PWM Interval Load Write 0h = Update the TAR register with the value in the TAILR register on the next clock cycle. If the pre-scaler is used, update the TAPS register with the value in the TAPR register on the next clock cycle. 1h = Update the TAR register with the value in the TAILR register on the next timeout. If the prescaler is used, update the TAPS register with the value in the TAPR register on the next timeout. |
| 7 | TASNAPS | R/W | 0h | GPT Timer A Snap-Shot Mode 0h = Snap-shot mode is disabled. 1h = If Timer A is configured in the periodic mode, the actual free-running value of Timer A is loaded at the time-out event into the GPT Timer A (TAR) register. |
| 6 | TAWOT | R/W | 0h | GPT Timer A Wait-On-Trigger 0h = Timer A begins counting as soon as it is enabled. 1h = If Timer A is enabled (CTL.TAEN = 1), Timer A does not begin counting until it receives a trigger from the timer in the previous position in the daisy chain. This bit must be clear for GPT Module 0, Timer A. This function is valid for one-shot, periodic, and PWM modes |
| 5 | TAMIE | R/W | 0h | GPT Timer A Match Interrupt Enable 0h = The match interrupt is disabled for match events. Additionally, output triggers on match events are prevented. 1h = An interrupt is generated when the match value in TAMATCHR is reached in the one-shot and periodic modes. |
| 4 | TACDIR | R/W | 0h | GPT Timer A Count Direction 0h = DOWN : The timer counts down. 1h = UP : The timer counts up. When counting up, the timer starts from a value of 0x0. |
| 3 | TAAMS | R/W | 0h | GPT Timer A Alternate Mode Note: To enable PWM mode, you must also clear TACM and then configure TAMR field to 0x2. 0h = Capture/Compare mode is enabled. 1h = PWM mode is enabled |
| 2 | TACM | R/W | 0h | GPT Timer A Capture Mode 0h = EDGCNT : Edge-Count mode 1h = EDGTIME : Edge-Time mode |
| 1-0 | TAMR | R/W | 0h | GPT Timer A Mode 0x0 Reserved 0x1 One-Shot Timer mode 0x2 Periodic Timer mode 0x3 Capture mode The Timer mode is based on the timer configuration defined by bits 2:0 in the CFG register 1h = One-Shot Timer mode 2h = Periodic Timer mode 3h = Capture mode |
TBMR is shown in #GPT_GPT_MAP1_GPT_ALL_TBMR_FIGURE and described in #GPT_GPT_MAP1_GPT_ALL_TBMR_TABLE.
Return to the Summary Table.
Timer B Mode
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| TCACT | TBCINTD | TBPLO | TBMRSU | TBPWMIE | TBILD | ||
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| TBSNAPS | TBWOT | TBMIE | TBCDIR | TBAMS | TBCM | TBMR | |
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-16 | RESERVED | R | 0h | Reserved |
| 15-13 | TCACT | R/W | 0h | Timer Compare Action Select 0h = DIS_CMP : Disable compare operations 1h = Toggle State on Time-Out 2h = Clear CCP output pin on Time-Out 3h = Set CCP output pin on Time-Out 4h = Set CCP output pin immediately and toggle on Time-Out 5h = Clear CCP output pin immediately and toggle on Time-Out 6h = Set CCP output pin immediately and clear on Time-Out 7h = Clear CCP output pin immediately and set on Time-Out |
| 12 | TBCINTD | R/W | 0h | One-Shot/Periodic Interrupt Mode 0h = Normal Time-Out Interrupt 1h = Mask Time-Out Interrupt |
| 11 | TBPLO | R/W | 0h | GPTM Timer B PWM Legacy Operation 0 Legacy operation with CCP pin driven Low when the TBILR register is reloaded after the timer reaches 0. 1 CCP is driven High when the TBILR register is reloaded after the timer reaches 0. This bit is only valid in PWM mode. 0h = Legacy operation 1h = CCP output pin is set to 1 on time-out |
| 10 | TBMRSU | R/W | 0h | Timer B Match Register Update mode This bit defines when the TBMATCHR and TBPR registers are updated If the timer is disabled (CTL.TBEN is clear) when this bit is set, TBMATCHR and TBPR are updated when the timer is enabled. If the timer is stalled (CTL.TBSTALL is set) when this bit is set, TBMATCHR and TBPR are updated according to the configuration of this bit. 0h = Update TBMATCHR and TBPR, if used, on the next cycle. 1h = Update TBMATCHR and TBPR, if used, on the next time-out. |
| 9 | TBPWMIE | R/W | 0h | GPTM Timer B PWM Interrupt Enable This bit enables interrupts in PWM mode on rising, falling, or both edges of the CCP output, as defined by the CTL.TBEVENT In addition, when this bit is set and a capture event occurs, Timer A automatically generates triggers to the DMA if the trigger capability is enabled by setting the CTL.TBOTE bit and the DMAEV.CBEDMAEN bit respectively. 0 Capture event interrupt is disabled. 1 Capture event interrupt is enabled. This bit is only valid in PWM mode. 0h = Interrupt is disabled. 1h = Interrupt is enabled. This bit is only valid in PWM mode. |
| 8 | TBILD | R/W | 0h | GPT Timer B PWM Interval Load Write 0h = Update the TBR register with the value in the TBILR register on the next clock cycle. If the pre-scaler is used, update the TBPS register with the value in the TBPR register on the next clock cycle. 1h = Update the TBR register with the value in the TBILR register on the next timeout. If the prescaler is used, update the TBPS register with the value in the TBPR register on the next timeout. |
| 7 | TBSNAPS | R/W | 0h | GPT Timer B Snap-Shot Mode 0h = Snap-shot mode is disabled. 1h = If Timer B is configured in the periodic mode |
| 6 | TBWOT | R/W | 0h | GPT Timer B Wait-On-Trigger 0h = Timer B begins counting as soon as it is enabled. 1h = If Timer B is enabled (CTL.TBEN is set), Timer B does not begin counting until it receives a trigger from the timer in the previous position in the daisy chain. This function is valid for one-shot, periodic, and PWM modes |
| 5 | TBMIE | R/W | 0h | GPT Timer B Match Interrupt Enable. 0h = The match interrupt is disabled for match events. Additionally, output triggers on match events are prevented. 1h = An interrupt is generated when the match value in the TBMATCHR register is reached in the one-shot and periodic modes. |
| 4 | TBCDIR | R/W | 0h | GPT Timer B Count Direction 0h = DOWN : The timer counts down. 1h = UP : The timer counts up. When counting up, the timer starts from a value of 0x0. |
| 3 | TBAMS | R/W | 0h | GPT Timer B Alternate Mode Note: To enable PWM mode, you must also clear TBCM bit and configure TBMR field to 0x2. 0h = Capture/Compare mode is enabled. 1h = PWM mode is enabled |
| 2 | TBCM | R/W | 0h | GPT Timer B Capture Mode 0h = EDGCNT : Edge-Count mode 1h = EDGTIME : Edge-Time mode |
| 1-0 | TBMR | R/W | 0h | GPT Timer B Mode 0x0 Reserved 0x1 One-Shot Timer mode 0x2 Periodic Timer mode 0x3 Capture mode The Timer mode is based on the timer configuration defined by bits 2:0 in the CFG register 1h = One-Shot Timer mode 2h = Periodic Timer mode 3h = Capture mode |
CTL is shown in #GPT_GPT_MAP1_GPT_ALL_CTL_FIGURE and described in #GPT_GPT_MAP1_GPT_ALL_CTL_TABLE.
Return to the Summary Table.
Control
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | TBPWML | RESERVED | TBEVENT | TBSTALL | TBEN | ||
| R-0h | R/W-0h | R-0h | R/W-0h | R/W-0h | R/W-0h | ||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | TAPWML | RESERVED | TAEVENT | TASTALL | TAEN | ||
| R-0h | R/W-0h | R-0h | R/W-0h | R/W-0h | R/W-0h | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-15 | RESERVED | R | 0h | Reserved |
| 14 | TBPWML | R/W | 0h | GPT Timer B PWM Output Level 0: Output is unaffected. 1: Output is inverted. 0h = Not inverted 1h = Inverted |
| 13-12 | RESERVED | R | 0h | Reserved |
| 11-10 | TBEVENT | R/W | 0h | GPT Timer B Event Mode The values in this register are defined as follows: Value Description 0x0 Positive edge 0x1 Negative edge 0x2 Reserved 0x3 Both edges Note: If PWM output inversion is enabled, edge detection interrupt behavior is reversed. Thus, if a positive-edge interrupt trigger has been set and the PWM inversion generates a postive edge, no event-trigger interrupt asserts. Instead, the interrupt is generated on the negative edge of the PWM signal. 0h = Positive edge 1h = Negative edge 3h = Both edges |
| 9 | TBSTALL | R/W | 0h | GPT Timer B Stall Enable 0h = Timer B continues counting while the processor is halted by the debugger. 1h = Timer B freezes counting while the processor is halted by the debugger. |
| 8 | TBEN | R/W | 0h | GPT Timer B Enable 0h = Timer B is disabled. 1h = Timer B is enabled and begins counting or the capture logic is enabled based on CFG register. |
| 7 | RESERVED | R | 0h | Reserved |
| 6 | TAPWML | R/W | 0h | GPT Timer A PWM Output Level 0h = Not inverted 1h = Inverted |
| 5-4 | RESERVED | R | 0h | Reserved |
| 3-2 | TAEVENT | R/W | 0h | GPT Timer A Event Mode The values in this register are defined as follows: Value Description 0x0 Positive edge 0x1 Negative edge 0x2 Reserved 0x3 Both edges Note: If PWM output inversion is enabled, edge detection interrupt behavior is reversed. Thus, if a positive-edge interrupt trigger has been set and the PWM inversion generates a postive edge, no event-trigger interrupt asserts. Instead, the interrupt is generated on the negative edge of the PWM signal. 0h = Positive edge 1h = Negative edge 3h = Both edges |
| 1 | TASTALL | R/W | 0h | GPT Timer A Stall Enable 0h = Timer A continues counting while the processor is halted by the debugger. 1h = Timer A freezes counting while the processor is halted by the debugger. |
| 0 | TAEN | R/W | 0h | GPT Timer A Enable 0h = Timer A is disabled. 1h = Timer A is enabled and begins counting or the capture logic is enabled based on the CFG register. |
SYNC is shown in #GPT_GPT_MAP1_GPT_ALL_SYNC_FIGURE and described in #GPT_GPT_MAP1_GPT_ALL_SYNC_TABLE.
Return to the Summary Table.
Synch Register
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||||||||||
| R-0h | |||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | SYNC3 | SYNC2 | SYNC1 | SYNC0 | |||||||||||
| R-0h | W-0h | W-0h | W-0h | W-0h | |||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-8 | RESERVED | R | 0h | Reserved |
| 7-6 | SYNC3 | W | 0h | Synchronize GPT Timer 3. 0h = No Sync. GPT3 is not affected. 1h = A timeout event for Timer A of GPT3 is triggered 2h = A timeout event for Timer B of GPT3 is triggered 3h = A timeout event for both Timer A and Timer B of GPT3 is triggered |
| 5-4 | SYNC2 | W | 0h | Synchronize GPT Timer 2. 0h = No Sync. GPT2 is not affected. 1h = A timeout event for Timer A of GPT2 is triggered 2h = A timeout event for Timer B of GPT2 is triggered 3h = A timeout event for both Timer A and Timer B of GPT2 is triggered |
| 3-2 | SYNC1 | W | 0h | Synchronize GPT Timer 1 0h = No Sync. GPT1 is not affected. 1h = A timeout event for Timer A of GPT1 is triggered 2h = A timeout event for Timer B of GPT1 is triggered 3h = A timeout event for both Timer A and Timer B of GPT1 is triggered |
| 1-0 | SYNC0 | W | 0h | Synchronize GPT Timer 0 0h = No Sync. GPT0 is not affected. 1h = A timeout event for Timer A of GPT0 is triggered 2h = A timeout event for Timer B of GPT0 is triggered 3h = A timeout event for both Timer A and Timer B of GPT0 is triggered |
IMR is shown in #GPT_GPT_MAP1_GPT_ALL_IMR_FIGURE and described in #GPT_GPT_MAP1_GPT_ALL_IMR_TABLE.
Return to the Summary Table.
Interrupt Mask
This register is used to enable the interrupts.
Associated registers:
RIS, MIS, ICLR
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | DMABIM | RESERVED | TBMIM | CBEIM | CBMIM | TBTOIM | |
| R-0h | R/W-0h | R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | DMAAIM | TAMIM | RESERVED | CAEIM | CAMIM | TATOIM | |
| R-0h | R/W-0h | R/W-0h | R-0h | R/W-0h | R/W-0h | R/W-0h | |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-14 | RESERVED | R | 0h | Reserved |
| 13 | DMABIM | R/W | 0h | Enabling this bit will make the RIS.DMABRIS interrupt
propagate to MIS.DMABMIS 0h = Disable Interrupt 1h = Enable Interrupt |
| 12 | RESERVED | R | 0h | Reserved |
| 11 | TBMIM | R/W | 0h | Enabling this bit will make the RIS.TBMRIS interrupt
propagate to MIS.TBMMIS 0h = Disable Interrupt 1h = Enable Interrupt |
| 10 | CBEIM | R/W | 0h | Enabling this bit will make the RIS.CBERIS interrupt
propagate to MIS.CBEMIS 0h = Disable Interrupt 1h = Enable Interrupt |
| 9 | CBMIM | R/W | 0h | Enabling this bit will make the RIS.CBMRIS interrupt
propagate to MIS.CBMMIS 0h = Disable Interrupt 1h = Enable Interrupt |
| 8 | TBTOIM | R/W | 0h | Enabling this bit will make the RIS.TBTORIS interrupt
propagate to MIS.TBTOMIS 0h = Disable Interrupt 1h = Enable Interrupt |
| 7-6 | RESERVED | R | 0h | Reserved |
| 5 | DMAAIM | R/W | 0h | Enabling this bit will make the RIS.DMAARIS interrupt
propagate to MIS.DMAAMIS 0h = Disable Interrupt 1h = Enable Interrupt |
| 4 | TAMIM | R/W | 0h | Enabling this bit will make the RIS.TAMRIS interrupt
propagate to MIS.TAMMIS 0h = Disable Interrupt 1h = Enable Interrupt |
| 3 | RESERVED | R | 0h | Reserved |
| 2 | CAEIM | R/W | 0h | Enabling this bit will make the RIS.CAERIS interrupt
propagate to MIS.CAEMIS 0h = Disable Interrupt 1h = Enable Interrupt |
| 1 | CAMIM | R/W | 0h | Enabling this bit will make the RIS.CAMRIS interrupt
propagate to MIS.CAMMIS 0h = Disable Interrupt 1h = Enable Interrupt |
| 0 | TATOIM | R/W | 0h | Enabling this bit will make the RIS.TATORIS interrupt
propagate to MIS.TATOMIS 0h = Disable Interrupt 1h = Enable Interrupt |
RIS is shown in #GPT_GPT_MAP1_GPT_ALL_RIS_FIGURE and described in #GPT_GPT_MAP1_GPT_ALL_RIS_TABLE.
Return to the Summary Table.
Raw Interrupt Status
Associated registers:
IMR, MIS, ICLR
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | DMABRIS | RESERVED | TBMRIS | CBERIS | CBMRIS | TBTORIS | |
| R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | DMAARIS | TAMRIS | RESERVED | CAERIS | CAMRIS | TATORIS | |
| R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-14 | RESERVED | R | 0h | Reserved |
| 13 | DMABRIS | R | 0h | GPT Timer B DMA Done Raw Interrupt Status 0: Transfer has not completed 1: Transfer has completed |
| 12 | RESERVED | R | 0h | Reserved |
| 11 | TBMRIS | R | 0h | GPT Timer B Match Raw Interrupt 0: The match value has not been reached 1: The match value is reached. TBMR.TBMIE is set, and the match values in TBMATCHR and optionally TBPMR have been reached when configured in one-shot or periodic mode. |
| 10 | CBERIS | R | 0h | GPT Timer B Capture Mode Event Raw Interrupt 0: The event has not occured. 1: The event has occured. This interrupt asserts when the subtimer is configured in Input Edge-Time mode |
| 9 | CBMRIS | R | 0h | GPT Timer B Capture Mode Match Raw Interrupt 0: The capture mode match for Timer B has not occurred. 1: A capture mode match has occurred for Timer B. This interrupt asserts when the values in the TBR and TBPR match the values in the TBMATCHR and TBPMR when configured in Input Edge-Time mode. This bit is cleared by writing a 1 to the ICLR.CBMCINT bit. |
| 8 | TBTORIS | R | 0h | GPT Timer B Time-out Raw Interrupt 0: Timer B has not timed out 1: Timer B has timed out. This interrupt is asserted when a one-shot or periodic mode timer reaches its count limit. The count limit is 0 or the value loaded into TBILR, depending on the count direction. |
| 7-6 | RESERVED | R | 0h | Reserved |
| 5 | DMAARIS | R | 0h | GPT Timer A DMA Done Raw Interrupt Status 0: Transfer has not completed 1: Transfer has completed |
| 4 | TAMRIS | R | 0h | GPT Timer A Match Raw Interrupt 0: The match value has not been reached 1: The match value is reached. TAMR.TAMIE is set, and the match values in TAMATCHR and optionally TAPMR have been reached when configured in one-shot or periodic mode. |
| 3 | RESERVED | R | 0h | Reserved |
| 2 | CAERIS | R | 0h | GPT Timer A Capture Mode Event Raw Interrupt 0: The event has not occured. 1: The event has occured. This interrupt asserts when the subtimer is configured in Input Edge-Time mode |
| 1 | CAMRIS | R | 0h | GPT Timer A Capture Mode Match Raw Interrupt 0: The capture mode match for Timer A has not occurred. 1: A capture mode match has occurred for Timer A. This interrupt asserts when the values in the TAR and TAPR match the values in the TAMATCHR and TAPMR when configured in Input Edge-Time mode. This bit is cleared by writing a 1 to the ICLR.CAMCINT bit. |
| 0 | TATORIS | R | 0h | GPT Timer A Time-out Raw Interrupt 0: Timer A has not timed out 1: Timer A has timed out. This interrupt is asserted when a one-shot or periodic mode timer reaches its count limit. The count limit is 0 or the value loaded into TAILR, depending on the count direction. |
MIS is shown in #GPT_GPT_MAP1_GPT_ALL_MIS_FIGURE and described in #GPT_GPT_MAP1_GPT_ALL_MIS_TABLE.
Return to the Summary Table.
Masked Interrupt Status
Values are result of bitwise AND operation between RIS
and IMR
Assosciated clear register: ICLR
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | DMABMIS | RESERVED | TBMMIS | CBEMIS | CBMMIS | TBTOMIS | |
| R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | DMAAMIS | TAMMIS | RESERVED | CAEMIS | CAMMIS | TATOMIS | |
| R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-14 | RESERVED | R | 0h | Reserved |
| 13 | DMABMIS | R | 0h | 0: No interrupt or interrupt not enabled 1: RIS.DMABRIS = 1 && IMR.DMABIM = 1 |
| 12 | RESERVED | R | 0h | Reserved |
| 11 | TBMMIS | R | 0h | 0: No interrupt or interrupt not enabled 1: RIS.TBMRIS = 1 && IMR.TBMIM = 1 |
| 10 | CBEMIS | R | 0h | 0: No interrupt or interrupt not enabled 1: RIS.CBERIS = 1 && IMR.CBEIM = 1 |
| 9 | CBMMIS | R | 0h | 0: No interrupt or interrupt not enabled 1: RIS.CBMRIS = 1 && IMR.CBMIM = 1 |
| 8 | TBTOMIS | R | 0h | 0: No interrupt or interrupt not enabled 1: RIS.TBTORIS = 1 && IMR.TBTOIM = 1 |
| 7-6 | RESERVED | R | 0h | Reserved |
| 5 | DMAAMIS | R | 0h | 0: No interrupt or interrupt not enabled 1: RIS.DMAARIS = 1 && IMR.DMAAIM = 1 |
| 4 | TAMMIS | R | 0h | 0: No interrupt or interrupt not enabled 1: RIS.TAMRIS = 1 && IMR.TAMIM = 1 |
| 3 | RESERVED | R | 0h | Reserved |
| 2 | CAEMIS | R | 0h | 0: No interrupt or interrupt not enabled 1: RIS.CAERIS = 1 && IMR.CAEIM = 1 |
| 1 | CAMMIS | R | 0h | 0: No interrupt or interrupt not enabled 1: RIS.CAMRIS = 1 && IMR.CAMIM = 1 |
| 0 | TATOMIS | R | 0h | 0: No interrupt or interrupt not enabled 1: RIS.TATORIS = 1 && IMR.TATOIM = 1 |
ICLR is shown in #GPT_GPT_MAP1_GPT_ALL_ICLR_FIGURE and described in #GPT_GPT_MAP1_GPT_ALL_ICLR_TABLE.
Return to the Summary Table.
Interrupt Clear
This register is used to clear status bits in the RIS
and MIS registers
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | DMABINT | RESERVED | TBMCINT | CBECINT | CBMCINT | TBTOCINT | |
| R-0h | R/W1C-0h | R-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | DMAAINT | TAMCINT | RESERVED | CAECINT | CAMCINT | TATOCINT | |
| R-0h | R/W1C-0h | R/W1C-0h | R-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-14 | RESERVED | R | 0h | Reserved |
| 13 | DMABINT | R/W1C | 0h | 0: Do nothing. 1: Clear RIS.DMABRIS and MIS.DMABMIS |
| 12 | RESERVED | R | 0h | Reserved |
| 11 | TBMCINT | R/W1C | 0h | 0: Do nothing. 1: Clear RIS.TBMRIS and MIS.TBMMIS |
| 10 | CBECINT | R/W1C | 0h | 0: Do nothing. 1: Clear RIS.CBERIS and MIS.CBEMIS |
| 9 | CBMCINT | R/W1C | 0h | 0: Do nothing. 1: Clear RIS.CBMRIS and MIS.CBMMIS |
| 8 | TBTOCINT | R/W1C | 0h | 0: Do nothing. 1: Clear RIS.TBTORIS and MIS.TBTOMIS |
| 7-6 | RESERVED | R | 0h | Reserved |
| 5 | DMAAINT | R/W1C | 0h | 0: Do nothing. 1: Clear RIS.DMAARIS and MIS.DMAAMIS |
| 4 | TAMCINT | R/W1C | 0h | 0: Do nothing. 1: Clear RIS.TAMRIS and MIS.TAMMIS |
| 3 | RESERVED | R | 0h | Reserved |
| 2 | CAECINT | R/W1C | 0h | 0: Do nothing. 1: Clear RIS.CAERIS and MIS.CAEMIS |
| 1 | CAMCINT | R/W1C | 0h | 0: Do nothing. 1: Clear RIS.CAMRIS and MIS.CAMMIS |
| 0 | TATOCINT | R/W1C | 0h | 0: Do nothing. 1: Clear RIS.TATORIS and MIS.TATOMIS |
TAILR is shown in #GPT_GPT_MAP1_GPT_ALL_TAILR_FIGURE and described in #GPT_GPT_MAP1_GPT_ALL_TAILR_TABLE.
Return to the Summary Table.
Timer A Interval Load Register
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| TAILR | |||||||||||||||||||||||||||||||
| R/W-FFFFFFFFh | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | TAILR | R/W | FFFFFFFFh | GPT Timer A Interval Load Register Writing this field loads the counter for Timer A. A read returns the current value of TAILR. |
TBILR is shown in #GPT_GPT_MAP1_GPT_ALL_TBILR_FIGURE and described in #GPT_GPT_MAP1_GPT_ALL_TBILR_TABLE.
Return to the Summary Table.
Timer B Interval Load Register
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| TBILR | |||||||||||||||||||||||||||||||
| R/W-FFFFh | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | TBILR | R/W | FFFFh | GPT Timer B Interval Load Register Writing this field loads the counter for Timer B. A read returns the current value of TBILR. |
TAMATCHR is shown in #GPT_GPT_MAP1_GPT_ALL_TAMATCHR_FIGURE and described in #GPT_GPT_MAP1_GPT_ALL_TAMATCHR_TABLE.
Return to the Summary Table.
Timer A Match Register
Interrupts can be generated when the timer value is
equal to the value in this register in one-shot or periodic mode.
In Edge-Count mode, this register along with TAILR,
determines how many edge events are counted.
The total
number of edge events counted is equal to the value in TAILR minus this value.
Note that in edge-count mode, when executing an
up-count, the value of TAPR and TAILR must be greater than the value of TAPMR and
this register.
In PWM mode, this value along with
TAILR, determines the duty cycle of the output PWM signal.
When a 16/32-bit GPT is configured to one of the
32-bit modes, TAMATCHR appears as a 32-bit register. (The upper 16-bits correspond
to the contents TBMATCHR).
In a 16-bit mode, the upper
16 bits of this register read as 0s and have no effect on the state of TBMATCHR.
Note : This register is updated internally (takes
effect) based on TAMR.TAMRSU
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| TAMATCHR | |||||||||||||||||||||||||||||||
| R/W-FFFFFFFFh | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | TAMATCHR | R/W | FFFFFFFFh | GPT Timer A Match Register |
TBMATCHR is shown in #GPT_GPT_MAP1_GPT_ALL_TBMATCHR_FIGURE and described in #GPT_GPT_MAP1_GPT_ALL_TBMATCHR_TABLE.
Return to the Summary Table.
Timer B Match Register
When a GPT is configured to one of the 32-bit modes,
the contents of bits 15:0 in this register are loaded into the upper 16 bits of
TAMATCHR.
Reads from this register return the
current match value of Timer B and writes are ignored.
In a 16-bit mode, bits 15:0 are used for the match value. Bits 31:16 are reserved
in both cases.
Note : This register is updated
internally (takes effect) based on TBMR.TBMRSU
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | TBMATCHR | ||||||||||||||||||||||||||||||
| R-0h | R/W-FFFFh | ||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-16 | RESERVED | R | 0h | Reserved |
| 15-0 | TBMATCHR | R/W | FFFFh | GPT Timer B Match Register |
TAPR is shown in #GPT_GPT_MAP1_GPT_ALL_TAPR_FIGURE and described in #GPT_GPT_MAP1_GPT_ALL_TAPR_TABLE.
Return to the Summary Table.
Timer A Pre-scale
This register allows software to extend the range of
the timers when they are used individually.
When in
one-shot or periodic down count modes, this register acts as a true prescaler for
the timer counter.
When acting as a true prescaler, the
prescaler counts down to 0 before the value in TAR and TAV registers are
incremented.
In all other individual/split modes,
this register is a linear extension of the upper range of the timer counter, holding
bits 23:16 in the 16-bit modes of the 16/32-bit GPT.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | TAPSR | ||||||||||||||||||||||||||||||
| R-0h | R/W-0h | ||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-8 | RESERVED | R | 0h | Reserved |
| 7-0 | TAPSR | R/W | 0h | Timer A Pre-scale. Prescaler ratio in one-shot and periodic count mode is TAPSR + 1, that is: 0: Prescaler ratio = 1 1: Prescaler ratio = 2 2: Prescaler ratio = 3 ... 255: Prescaler ratio = 256 |
TBPR is shown in #GPT_GPT_MAP1_GPT_ALL_TBPR_FIGURE and described in #GPT_GPT_MAP1_GPT_ALL_TBPR_TABLE.
Return to the Summary Table.
Timer B Pre-scale
This register allows software to extend the range of
the timers when they are used individually.
When in
one-shot or periodic down count modes, this register acts as a true prescaler for
the timer counter.
When acting as a true prescaler, the
prescaler counts down to 0 before the value in TBR and TBV registers are
incremented.
In all other individual/split modes,
this register is a linear extension of the upper range of the timer counter, holding
bits 23:16 in the 16-bit modes of the 16/32-bit GPT.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | TBPSR | ||||||||||||||||||||||||||||||
| R-0h | R/W-0h | ||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-8 | RESERVED | R | 0h | Reserved |
| 7-0 | TBPSR | R/W | 0h | Timer B Pre-scale. Prescale ratio in one-shot and periodic count mode is TBPSR + 1, that is: 0: Prescaler ratio = 1 1: Prescaler ratio = 2 2: Prescaler ratio = 3 ... 255: Prescaler ratio = 256 |
TAPMR is shown in #GPT_GPT_MAP1_GPT_ALL_TAPMR_FIGURE and described in #GPT_GPT_MAP1_GPT_ALL_TAPMR_TABLE.
Return to the Summary Table.
Timer A Pre-scale Match
This register allows software to extend the range of
the TAMATCHR when used individually.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | TAPSMR | ||||||||||||||||||||||||||||||
| R-0h | R/W-0h | ||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-8 | RESERVED | R | 0h | Reserved |
| 7-0 | TAPSMR | R/W | 0h | GPT Timer A Pre-scale Match. In 16 bit mode this field holds bits 23 to 16. |
TBPMR is shown in #GPT_GPT_MAP1_GPT_ALL_TBPMR_FIGURE and described in #GPT_GPT_MAP1_GPT_ALL_TBPMR_TABLE.
Return to the Summary Table.
Timer B Pre-scale Match
This register allows software to extend the range of
the TBMATCHR when used individually.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | TBPSMR | ||||||||||||||||||||||||||||||
| R-0h | R/W-0h | ||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-8 | RESERVED | R | 0h | Reserved |
| 7-0 | TBPSMR | R/W | 0h | GPT Timer B Pre-scale Match Register. In 16 bit mode this field holds bits 23 to 16. |
TAR is shown in #GPT_GPT_MAP1_GPT_ALL_TAR_FIGURE and described in #GPT_GPT_MAP1_GPT_ALL_TAR_TABLE.
Return to the Summary Table.
Timer A Register
This register shows the current value of the Timer A
counter in all cases except for Input Edge Count and Time modes. In the Input Edge
Count mode, this register contains the number of edges that
have occurred. In the Input Edge Time mode, this
register contains the time at which the last edge event took place.
When a GPT is configured to one of the 32-bit modes,
this register appears as a 32-bit register (the upper 16-bits correspond to the
contents of the Timer B (TBR) register). In
the16-bit
Input Edge Count, Input Edge Time, and PWM modes, bits 15:0 contain the value of the
counter and bits 23:16 contain the value of the prescaler, which is the upper 8 bits
of the count. Bits
31:24 always read as 0. To read the
value of the prescaler in 16-bit One-Shot and Periodic modes, read bits [23:16] in
the TAV register. To read the value of the prescalar in periodic snapshot
mode, read the Timer A Prescale Snapshot (TAPS)
register.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| TAR | |||||||||||||||||||||||||||||||
| R-FFFFFFFFh | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | TAR | R | FFFFFFFFh | GPT Timer A Register Based on the value in the register field TAMR.TAILD, this register is updated with the value from TAILR register either on the next cycle or on the next timeout. A read returns the current value of the Timer A Count Register, in all cases except for Input Edge count and Timer modes. In the Input Edge Count Mode, this register contains the number of edges that have occurred. In the Input Edge Time mode, this register contains the time at which the last edge event took place. |
TBR is shown in #GPT_GPT_MAP1_GPT_ALL_TBR_FIGURE and described in #GPT_GPT_MAP1_GPT_ALL_TBR_TABLE.
Return to the Summary Table.
Timer B Register
This register shows the current value of the Timer B
counter in all cases except for Input Edge Count and Time modes. In the Input Edge
Count mode, this register contains the number of edges that
have occurred. In the Input Edge Time mode, this
register contains the time at which the last edge event took place.
When a GPTM is configured to one of the 32-bit modes,
the contents of bits 15:0 in this register are loaded into the upper 16 bits of the
TAR register. Reads from this register return the current
value of Timer B. In a 16-bit mode, bits 15:0 contain
the value of the counter and bits 23:16 contain the value of the prescaler in Input
Edge Count, Input Edge Time, and PWM modes, which is the
upper 8 bits of the count. Bits 31:24 always read as 0. To read the value of the
prescaler in 16-bit One-Shot and Periodic modes, read bits [23:16] in the TBV
register. To read the value of the
prescalar in
periodic snapshot mode, read the Timer B Prescale Snapshot (TBPS) register.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| TBR | |||||||||||||||||||||||||||||||
| R-FFFFh | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | TBR | R | FFFFh | GPT Timer B Register Based on the value in the register field TBMR.TBILD, this register is updated with the value from TBILR register either on the next cycle or on the next timeout. A read returns the current value of the Timer B Count Register, in all cases except for Input Edge count and Timer modes. In the Input Edge Count Mode, this register contains the number of edges that have occurred. In the Input Edge Time mode, this register contains the time at which the last edge event took place. |
TAV is shown in #GPT_GPT_MAP1_GPT_ALL_TAV_FIGURE and described in #GPT_GPT_MAP1_GPT_ALL_TAV_TABLE.
Return to the Summary Table.
Timer A Value
When read, this register shows the current,
free-running value of Timer A in all modes. Softwarecan use this value to determine
the time elapsed between an interrupt and the ISR entry when using
the snapshot feature with the periodic operating mode.
When written, the value written into this register is loaded into the TAR register
on the next clock cycle.
When a 16/32-bit GPTM is
configured to one of the 32-bit modes, this register appears as a 32-bit register
(the upper 16-bits correspond to the contents of the GPTM Timer B Value (TBV)
register). In a 16-bit mode, bits 15:0 contain the value of the counter and bits
23:16 contain the current, free-running value of the prescaler, which is the upper 8
bits of the count in Input Edge Count, Input Edge Time, PWM and one-shot or periodic
up count modes. In one-shot or periodic
down count
modes, the prescaler stored in 23:16 is a true prescaler, meaning bits 23:16 count
down before decrementing the value in bits 15:0. The prescaler in bits 31:24 always
reads as 0.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| TAV | |||||||||||||||||||||||||||||||
| R/W-FFFFFFFFh | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | TAV | R/W | FFFFFFFFh | GPT Timer A Register A read returns the current, free-running value of Timer A in all modes. When written, the value written into this register is loaded into the TAR register on the next clock cycle. Note: In 16-bit mode, only the lower 16-bits of this register can be written with a new value. Writes to the prescaler bits have no effect |
TBV is shown in #GPT_GPT_MAP1_GPT_ALL_TBV_FIGURE and described in #GPT_GPT_MAP1_GPT_ALL_TBV_TABLE.
Return to the Summary Table.
Timer B Value
When read, this register shows the current,
free-running value of Timer B in all modes. Software can use this value to determine
the time elapsed between an interrupt and the ISR entry. When
written, the value written into this register is
loaded into the TBR register on the next clock cycle.
When a 16/32-bit GPTM is configured to one of the 32-bit modes, the contents of
bits 15:0 in this register are loaded into the upper 16 bits of the TAV register.
Reads from this register return
the current
free-running value of Timer B. In a 16-bit mode, bits 15:0 contain the value of the
counter and bits 23:16 contain the current, free-running value of the prescaler,
which is the upper 8 bits of
the count in Input Edge
Count, Input Edge Time, PWM and one-shot or periodic up count modes.
In one-shot or periodic down count modes, the
prescaler stored in 23:16 is a true prescaler, meaning bits 23:16 count down before
decrementing the value in bits 15:0. The prescaler in bits 31:24 always reads as
0.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| TBV | |||||||||||||||||||||||||||||||
| R/W-FFFFh | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | TBV | R/W | FFFFh | GPT Timer B Register A read returns the current, free-running value of Timer B in all modes. When written, the value written into this register is loaded into the TBR register on the next clock cycle. Note: In 16-bit mode, only the lower 16-bits of this register can be written with a new value. Writes to the prescaler bits have no effect |
TAPS is shown in #GPT_GPT_MAP1_GPT_ALL_TAPS_FIGURE and described in #GPT_GPT_MAP1_GPT_ALL_TAPS_TABLE.
Return to the Summary Table.
Timer A Pre-scale Snap-shot
Based on the value in the register field TAMR.TAILD,
this register is updated with the value from TAPR register either on the next cycle
or on the next timeout.
This register shows the current
value of the Timer A pre-scaler in the 16-bit mode.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PSS | ||||||||||||||||||||||||||||||
| R-0h | R-0h | ||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-8 | RESERVED | R | 0h | Reserved |
| 7-0 | PSS | R | 0h | GPT Timer A Pre-scaler |
TBPS is shown in #GPT_GPT_MAP1_GPT_ALL_TBPS_FIGURE and described in #GPT_GPT_MAP1_GPT_ALL_TBPS_TABLE.
Return to the Summary Table.
Timer B Pre-scale Snap-shot
Based on the value in the register field TBMR.TBILD,
this register is updated with the value from TBPR register either on the next cycle
or on the next timeout.
This register shows the current
value of the Timer B pre-scaler in the 16-bit mode.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PSS | ||||||||||||||||||||||||||||||
| R-0h | R-0h | ||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-8 | RESERVED | R | 0h | Reserved |
| 7-0 | PSS | R | 0h | GPT Timer B Pre-scaler |
TAPV is shown in #GPT_GPT_MAP1_GPT_ALL_TAPV_FIGURE and described in #GPT_GPT_MAP1_GPT_ALL_TAPV_TABLE.
Return to the Summary Table.
Timer A Pre-scale Value
This register shows the current value of the Timer A
free running pre-scaler in the 16-bit mode.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PSV | ||||||||||||||||||||||||||||||
| R-0h | R-0h | ||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-8 | RESERVED | R | 0h | Reserved |
| 7-0 | PSV | R | 0h | GPT Timer A Pre-scaler Value |
TBPV is shown in #GPT_GPT_MAP1_GPT_ALL_TBPV_FIGURE and described in #GPT_GPT_MAP1_GPT_ALL_TBPV_TABLE.
Return to the Summary Table.
Timer B Pre-scale Value
This register shows the current value of the Timer B
free running pre-scaler in the 16-bit mode.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PSV | ||||||||||||||||||||||||||||||
| R-0h | R-0h | ||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-8 | RESERVED | R | 0h | Reserved |
| 7-0 | PSV | R | 0h | GPT Timer B Pre-scaler Value |
DMAEV is shown in #GPT_GPT_MAP1_GPT_ALL_DMAEV_FIGURE and described in #GPT_GPT_MAP1_GPT_ALL_DMAEV_TABLE.
Return to the Summary Table.
DMA Event
This register allows software to enable/disable GPT DMA trigger events.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | TBMDMAEN | CBEDMAEN | CBMDMAEN | TBTODMAEN | |||
| R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | TAMDMAEN | RESERVED | CAEDMAEN | CAMDMAEN | TATODMAEN | ||
| R/W-0h | R/W-0h | R-0h | R/W-0h | R/W-0h | R/W-0h | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-12 | RESERVED | R | 0h | Software should not rely on the value of a reserved field. Writing any other value may result in undefined behavior. |
| 11 | TBMDMAEN | R/W | 0h | GPT Timer B Match DMA Trigger Enable |
| 10 | CBEDMAEN | R/W | 0h | GPT Timer B Capture Event DMA Trigger Enable |
| 9 | CBMDMAEN | R/W | 0h | GPT Timer B Capture Match DMA Trigger Enable |
| 8 | TBTODMAEN | R/W | 0h | GPT Timer B Time-Out DMA Trigger Enable |
| 7-5 | RESERVED | R/W | 0h | Software should not rely on the value of a reserved field. Writing any other value may result in undefined behavior. |
| 4 | TAMDMAEN | R/W | 0h | GPT Timer A Match DMA Trigger Enable |
| 3 | RESERVED | R | 0h | Reserved |
| 2 | CAEDMAEN | R/W | 0h | GPT Timer A Capture Event DMA Trigger Enable |
| 1 | CAMDMAEN | R/W | 0h | GPT Timer A Capture Match DMA Trigger Enable |
| 0 | TATODMAEN | R/W | 0h | GPT Timer A Time-Out DMA Trigger Enable |
VERSION is shown in #GPT_GPT_MAP1_GPT_ALL_VERSION_FIGURE and described in #GPT_GPT_MAP1_GPT_ALL_VERSION_TABLE.
Return to the Summary Table.
Peripheral Version
This register provides information regarding the GPT
version
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| VERSION | |||||||||||||||||||||||||||||||
| R-400h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | VERSION | R | 400h | Timer Revision. |
ANDCCP is shown in #GPT_GPT_MAP1_GPT_ALL_ANDCCP_FIGURE and described in #GPT_GPT_MAP1_GPT_ALL_ANDCCP_TABLE.
Return to the Summary Table.
Combined CCP Output
This register is used to logically AND CCP output
pairs for each timer
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | LD_TO_EN | CCP_AND_EN | |||||
| R-0h | R/W-0h | R/W-0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-2 | RESERVED | R | 0h | Reserved |
| 1 | LD_TO_EN | R/W | 0h | PWM assertion would happen at timeout 0: PWM assertion happens when counter matches load value 1: PWM assertion happens at timeout of the counter |
| 0 | CCP_AND_EN | R/W | 0h | Enables AND operation of the CCP outputs for timers A
and B. 0 : PWM outputs of Timer A and Timer B are the internal generated PWM signals of the respective timers. 1 : PWM output of Timer A is ANDed version of Timer A and Timer B PWM signals and Timer B PWM ouput is Timer B PWM signal only. |