SWCU192 November   2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7

 

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    9.     402
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  14.   404
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    4.     448
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    5.     454
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  16.   456
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    3.     459
      1.      460
      2.      461
        1.       462
        2.       463
        3.       464
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        5.       466
      3.      467
      4.      468
    4.     469
      1.      470
      2.      471
      3.      472
      4.      473
      5.      474
    5.     475
      1.      476
  17.   477
    1.     478
    2.     479
      1.      480
      2.      481
      3.      482
        1.       483
      4.      484
    3.     485
      1.      486
      2.      487
      3.      488
    4.     489
      1.      490
  18.   491
    1.     492
    2.     493
    3.     494
    4.     495
      1.      496
  19.   497
    1.     498
    2.     499
    3.     500
    4.     501
    5.     502
      1.      503
      2.      504
      3.      505
    6.     506
      1.      507
        1.       508
        2.       509
        3.       510
          1.        511
          2.        512
    7.     513
      1.      514
  20.   515
    1.     516
      1.      517
    2.     518
      1.      519
        1.       520
      2.      521
        1.       522
        2.       523
      3.      524
      4.      525
    3.     526
      1.      527
        1.       528
        2.       529
        3.       530
        4.       531
      2.      532
        1.       533
          1.        534
        2.       535
          1.        536
          2.        537
        3.       538
          1.        539
        4.       540
          1.        541
          2.        542
          3.        543
        5.       544
        6.       545
        7.       546
        8.       547
        9.       548
        10.       549
    4.     550
      1.      551
        1.       552
      2.      553
        1.       554
        2.       555
          1.        556
          2.        557
          3.        558
          4.        559
          5.        560
      3.      561
        1.       562
        2.       563
        3.       564
      4.      565
        1.       566
        2.       567
          1.        568
          2.        569
          3.        570
      5.      571
        1.       572
        2.       573
          1.        574
          2.        575
          3.        576
          4.        577
            1.         578
            2.         579
          5.        580
          6.        581
        3.       582
          1.        583
          2.        584
          3.        585
            1.         586
            2.         587
            3.         588
            4.         589
          4.        590
      6.      591
        1.       592
        2.       593
      7.      594
        1.       595
        2.       596
          1.        597
          2.        598
          3.        599
          4.        600
          5.        601
            1.         602
              1.          603
            2.         604
              1.          605
            3.         606
              1.          607
          6.        608
    5.     609
      1.      610
        1.       611
        2.       612
      2.      613
        1.       614
        2.       615
          1.        616
          2.        617
          3.        618
          4.        619
          5.        620
          6.        621
          7.        622
          8.        623
      3.      624
        1.       625
        2.       626
          1.        627
          2.        628
          3.        629
          4.        630
      4.      631
        1.       632
        2.       633
          1.        634
          2.        635
          3.        636
            1.         637
            2.         638
      5.      639
        1.       640
        2.       641
          1.        642
          2.        643
          3.        644
            1.         645
            2.         646
            3.         647
          4.        648
            1.         649
            2.         650
            3.         651
            4.         652
          5.        653
          6.        654
      6.      655
        1.       656
        2.       657
          1.        658
          2.        659
          3.        660
          4.        661
          5.        662
    6.     663
      1.      664
        1.       665
        2.       666
          1.        667
            1.         668
            2.         669
      2.      670
      3.      671
      4.      672
      5.      673
      6.      674
      7.      675
    7.     676
    8.     677
      1.      678
      2.      679
      3.      680
      4.      681
      5.      682
      6.      683
      7.      684
      8.      685
      9.      686
      10.      687
      11.      688
      12.      689
  21.   690
    1.     691
    2.     692
    3.     693
      1.      694
  22.   695
    1.     696
    2.     697
    3.     698
    4.     699
      1.      700
      2.      701
      3.      702
      4.      703
        1.       704
        2.       705
          1.        706
          2.        707
      5.      708
      6.      709
      7.      710
    5.     711
    6.     712
    7.     713
      1.      714
  23.   715
    1.     716
    2.     717
    3.     718
    4.     719
      1.      720
      2.      721
        1.       722
        2.       723
      3.      724
      4.      725
        1.       726
        2.       727
          1.        728
          2.        729
        3.       730
        4.       731
        5.       732
        6.       733
        7.       734
    5.     735
    6.     736
    7.     737
      1.      738
  24.   739
    1.     740
    2.     741
    3.     742
      1.      743
        1.       744
        2.       745
        3.       746
        4.       747
        5.       748
      2.      749
        1.       750
      3.      751
        1.       752
        2.       753
      4.      754
      5.      755
        1.       756
        2.       757
    4.     758
    5.     759
      1.      760
  25.   761
    1.     762
    2.     763
    3.     764
    4.     765
      1.      766
        1.       767
      2.      768
      3.      769
      4.      770
        1.       771
      5.      772
        1.       773
      6.      774
        1.       775
      7.      776
        1.       777
      8.      778
        1.       779
        2.       780
    5.     781
      1.      782
      2.      783
      3.      784
      4.      785
        1.       786
        2.       787
        3.       788
    6.     789
      1.      790
      2.      791
      3.      792
      4.      793
    7.     794
    8.     795
      1.      796
      2.      797
    9.     798
      1.      799
  26.   800
    1.     801
      1.      802
    2.     803
      1.      804
      2.      805
      3.      806
        1.       807
        2.       808
        3.       809
      4.      810
        1.       811
        2.       812
        3.       813
    3.     814
      1.      815
      2.      816
        1.       817
        2.       818
        3.       819
        4.       820
        5.       821
          1.        822
          2.        823
          3.        824
        6.       825
          1.        826
        7.       827
          1.        828
          2.        829
          3.        830
          4.        831
        8.       832
      3.      833
        1.       834
          1.        835
          2.        836
          3.        837
          4.        838
          5.        839
          6.        840
          7.        841
          8.        842
          9.        843
          10.        844
          11.        845
          12.        846
          13.        847
          14.        848
        2.       849
          1.        850
          2.        851
          3.        852
          4.        853
          5.        854
          6.        855
          7.        856
          8.        857
          9.        858
          10.        859
          11.        860
          12.        861
          13.        862
          14.        863
          15.        864
          16.        865
          17.        866
          18.        867
          19.        868
          20.        869
      4.      870
        1.       871
        2.       872
        3.       873
        4.       874
        5.       875
    4.     876
      1.      877
        1.       878
        2.       879
        3.       880
        4.       881
        5.       882
      2.      883
        1.       884
        2.       885
    5.     886
      1.      887
        1.       888
        2.       889
        3.       890
        4.       891
      2.      892
      3.      893
        1.       894
        2.       895
      4.      896
        1.       897
          1.        898
            1.         899
            2.         900
          2.        901
          3.        902
          4.        903
          5.        904
        2.       905
        3.       906
        4.       907
        5.       908
        6.       909
      5.      910
        1.       911
        2.       912
        3.       913
        4.       914
        5.       915
        6.       916
    6.     917
      1.      918
        1.       919
          1.        920
        2.       921
        3.       922
        4.       923
      2.      924
    7.     925
      1.      926
      2.      927
    8.     928
      1.      929
      2.      930
      3.      931
      4.      932
      5.      933
      6.      934
      7.      935
      8.      936
        1.       937
        2.       938
        3.       939
        4.       940
      9.      941
        1.       942
        2.       943
        3.       944
      10.      945
        1.       946
        2.       947
        3.       948
        4.       949
        5.       950
      11.      951
        1.       952
        2.       953
        3.       954
        4.       955
        5.       956
      12.      957
      13.      958
      14.      959
      15.      960
      16.      961
      17.      962
    9.     963
      1.      964
    10.     965
      1.      966
      2.      967
        1.       968
          1.        969
        2.       970
        3.       971
      3.      972
      4.      973
        1.       974
        2.       975
      5.      976
        1.       977
        2.       978
          1.        979
        3.       980
          1.        981
          2.        982
        4.       983
          1.        984
          2.        985
        5.       986
          1.        987
          2.        988
          3.        989
      6.      990
        1.       991
        2.       992
    11.     993
      1.      994
      2.      995
      3.      996
  27.   997

15.5.1 µDMA Registers

#DMA_PL230_R0P0_DMA_PL230_R0P0_MAP1_TABLE_1 lists the memory-mapped registers for the µDMA registers. All register offset addresses not listed in #DMA_PL230_R0P0_DMA_PL230_R0P0_MAP1_TABLE_1 should be considered as reserved locations and the register contents should not be modified.

Table 15-7 µDMA Registers
Offset Acronym Register Name Section
0h STATUS Status #DMA_PL230_R0P0_DMA_PL230_R0P0_MAP1_DMA_PL230_R0P0_ALL_STATUS
4h CFG Configuration #DMA_PL230_R0P0_DMA_PL230_R0P0_MAP1_DMA_PL230_R0P0_ALL_CFG
8h CTRL Channel Control Data Base Pointer #DMA_PL230_R0P0_DMA_PL230_R0P0_MAP1_DMA_PL230_R0P0_ALL_CTRL
Ch ALTCTRL Channel Alternate Control Data Base Pointer #DMA_PL230_R0P0_DMA_PL230_R0P0_MAP1_DMA_PL230_R0P0_ALL_ALTCTRL
10h WAITONREQ Channel Wait On Request Status #DMA_PL230_R0P0_DMA_PL230_R0P0_MAP1_DMA_PL230_R0P0_ALL_WAITONREQ
14h SOFTREQ Channel Software Request #DMA_PL230_R0P0_DMA_PL230_R0P0_MAP1_DMA_PL230_R0P0_ALL_SOFTREQ
18h SETBURST Channel Set UseBurst #DMA_PL230_R0P0_DMA_PL230_R0P0_MAP1_DMA_PL230_R0P0_ALL_SETBURST
1Ch CLEARBURST Channel Clear UseBurst #DMA_PL230_R0P0_DMA_PL230_R0P0_MAP1_DMA_PL230_R0P0_ALL_CLEARBURST
20h SETREQMASK Channel Set Request Mask #DMA_PL230_R0P0_DMA_PL230_R0P0_MAP1_DMA_PL230_R0P0_ALL_SETREQMASK
24h CLEARREQMASK Clear Channel Request Mask #DMA_PL230_R0P0_DMA_PL230_R0P0_MAP1_DMA_PL230_R0P0_ALL_CLEARREQMASK
28h SETCHANNELEN Set Channel Enable #DMA_PL230_R0P0_DMA_PL230_R0P0_MAP1_DMA_PL230_R0P0_ALL_SETCHANNELEN
2Ch CLEARCHANNELEN Clear Channel Enable #DMA_PL230_R0P0_DMA_PL230_R0P0_MAP1_DMA_PL230_R0P0_ALL_CLEARCHANNELEN
30h SETCHNLPRIALT Channel Set Primary-Alternate #DMA_PL230_R0P0_DMA_PL230_R0P0_MAP1_DMA_PL230_R0P0_ALL_SETCHNLPRIALT
34h CLEARCHNLPRIALT Channel Clear Primary-Alternate #DMA_PL230_R0P0_DMA_PL230_R0P0_MAP1_DMA_PL230_R0P0_ALL_CLEARCHNLPRIALT
38h SETCHNLPRIORITY Set Channel Priority #DMA_PL230_R0P0_DMA_PL230_R0P0_MAP1_DMA_PL230_R0P0_ALL_SETCHNLPRIORITY
3Ch CLEARCHNLPRIORITY Clear Channel Priority #DMA_PL230_R0P0_DMA_PL230_R0P0_MAP1_DMA_PL230_R0P0_ALL_CLEARCHNLPRIORITY
4Ch ERROR Error Status and Clear #DMA_PL230_R0P0_DMA_PL230_R0P0_MAP1_DMA_PL230_R0P0_ALL_ERROR
504h REQDONE Channel Request Done #DMA_PL230_R0P0_DMA_PL230_R0P0_MAP1_DMA_PL230_R0P0_ALL_REQDONE
520h DONEMASK Channel Request Done Mask #DMA_PL230_R0P0_DMA_PL230_R0P0_MAP1_DMA_PL230_R0P0_ALL_DONEMASK

Complex bit access types are encoded to fit into small table cells. #DMA_PL230_R0P0_DMA_PL230_R0P0_MAP1_LEGEND shows the codes that are used for access types in this section.

Table 15-8 µDMA Access Type Codes
Access Type Code Description
Read Type
R R Read
Write Type
W W Write
Reset or Default Value
-n Value after reset or the default value

15.5.1.1 STATUS Register (Offset = 0h) [Reset = 001F0000h]

STATUS is shown in #DMA_PL230_R0P0_DMA_PL230_R0P0_MAP1_DMA_PL230_R0P0_ALL_STATUS_FIGURE and described in #DMA_PL230_R0P0_DMA_PL230_R0P0_MAP1_DMA_PL230_R0P0_ALL_STATUS_TABLE.

Return to the Summary Table.

Status

Figure 15-7 STATUS Register
31 30 29 28 27 26 25 24
TEST RESERVED
R-0h R-0h
23 22 21 20 19 18 17 16
RESERVED TOTALCHANNELS
R-0h R-1Fh
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
STATE RESERVED MASTERENABLE
R-0h R-0h R-0h
Table 15-9 STATUS Register Field Descriptions
Bit Field Type Reset Description
31-28 TEST R 0h
0x0: Controller does not include the integration test logic
0x1: Controller includes the integration test logic
0x2: Undefined
...
0xF: Undefined
27-21 RESERVED R 0h Reserved
20-16 TOTALCHANNELS R 1Fh Register value returns number of available uDMA channels minus one. For example a read out value of:
0x00: Show that the controller is configured to use 1 uDMA channel
0x01: Shows that the controller is configured to use 2 uDMA channels
...
0x1F: Shows that the controller is configured to use 32 uDMA channels (32-1=31=0x1F)
15-8 RESERVED R 0h Reserved
7-4 STATE R 0h Current state of the control state machine. State can be one of the following:
0x0: Idle
0x1: Reading channel controller data
0x2: Reading source data end pointer
0x3: Reading destination data end pointer
0x4: Reading source data
0x5: Writing destination data
0x6: Waiting for uDMA request to clear
0x7: Writing channel controller data
0x8: Stalled
0x9: Done
0xA: Peripheral scatter-gather transition
0xB: Undefined
...
0xF: Undefined.
3-1 RESERVED R 0h Reserved
0 MASTERENABLE R 0h Shows the enable status of the controller as configured by CFG.MASTERENABLE:
0: Controller is disabled
1: Controller is enabled

15.5.1.2 CFG Register (Offset = 4h) [Reset = 00000000h]

CFG is shown in #DMA_PL230_R0P0_DMA_PL230_R0P0_MAP1_DMA_PL230_R0P0_ALL_CFG_FIGURE and described in #DMA_PL230_R0P0_DMA_PL230_R0P0_MAP1_DMA_PL230_R0P0_ALL_CFG_TABLE.

Return to the Summary Table.

Configuration

Figure 15-8 CFG Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
PRTOCTRL RESERVED MASTERENABLE
W-0h R-0h W-0h
Table 15-10 CFG Register Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R 0h Reserved
7-5 PRTOCTRL W 0h Sets the AHB-Lite bus protocol protection state by controlling the AHB signal HProt[3:1] as follows:
Bit [7] Controls HProt[3] to indicate if a cacheable access is occurring.
Bit [6] Controls HProt[2] to indicate if a bufferable access is occurring.
Bit [5] Controls HProt[1] to indicate if a privileged access is occurring.
When bit [n] = 1 then the corresponding HProt bit is high.
When bit [n] = 0 then the corresponding HProt bit is low.
This field controls HProt[3:1] signal for all transactions initiated by uDMA except two transactions below:
- the read from the address indicated by source address pointer
- the write to the address indicated by destination address pointer
HProt[3:1] for these two exceptions can be controlled by dedicated fields in the channel configutation descriptor.
4-1 RESERVED R 0h Reserved
0 MASTERENABLE W 0h Enables the controller:
0: Disables the controller
1: Enables the controller

15.5.1.3 CTRL Register (Offset = 8h) [Reset = 00000000h]

CTRL is shown in #DMA_PL230_R0P0_DMA_PL230_R0P0_MAP1_DMA_PL230_R0P0_ALL_CTRL_FIGURE and described in #DMA_PL230_R0P0_DMA_PL230_R0P0_MAP1_DMA_PL230_R0P0_ALL_CTRL_TABLE.

Return to the Summary Table.

Channel Control Data Base Pointer

Figure 15-9 CTRL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BASEPTR RESERVED
R/W-0h R-0h
Table 15-11 CTRL Register Field Descriptions
Bit Field Type Reset Description
31-10 BASEPTR R/W 0h This register point to the base address for the primary data structures of each DMA channel. This is not stored in module, but in system memory, thus space must be allocated for this usage when DMA is in usage
9-0 RESERVED R 0h Reserved

15.5.1.4 ALTCTRL Register (Offset = Ch) [Reset = 00000200h]

ALTCTRL is shown in #DMA_PL230_R0P0_DMA_PL230_R0P0_MAP1_DMA_PL230_R0P0_ALL_ALTCTRL_FIGURE and described in #DMA_PL230_R0P0_DMA_PL230_R0P0_MAP1_DMA_PL230_R0P0_ALL_ALTCTRL_TABLE.

Return to the Summary Table.

Channel Alternate Control Data Base Pointer

Figure 15-10 ALTCTRL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BASEPTR
R-200h
Table 15-12 ALTCTRL Register Field Descriptions
Bit Field Type Reset Description
31-0 BASEPTR R 200h This register shows the base address for the alternate data structures and is calculated by module, thus read only

15.5.1.5 WAITONREQ Register (Offset = 10h) [Reset = FFFF1EFFh]

WAITONREQ is shown in #DMA_PL230_R0P0_DMA_PL230_R0P0_MAP1_DMA_PL230_R0P0_ALL_WAITONREQ_FIGURE and described in #DMA_PL230_R0P0_DMA_PL230_R0P0_MAP1_DMA_PL230_R0P0_ALL_WAITONREQ_TABLE.

Return to the Summary Table.

Channel Wait On Request Status

Figure 15-11 WAITONREQ Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CHNLSTATUS
R-FFFF1EFFh
Table 15-13 WAITONREQ Register Field Descriptions
Bit Field Type Reset Description
31-0 CHNLSTATUS R FFFF1EFFh Channel wait on request status:
Bit [Ch] = 0: Once uDMA receives a single or burst request on channel Ch, this channel may come out of active state even if request is still present.
Bit [Ch] = 1: Once uDMA receives a single or burst request on channel Ch, it keeps channel Ch in active state until the requests are deasserted. This handshake is necessary for channels where the requester is in an asynchronous domain or can run at slower clock speed than uDMA

15.5.1.6 SOFTREQ Register (Offset = 14h) [Reset = 00000000h]

SOFTREQ is shown in #DMA_PL230_R0P0_DMA_PL230_R0P0_MAP1_DMA_PL230_R0P0_ALL_SOFTREQ_FIGURE and described in #DMA_PL230_R0P0_DMA_PL230_R0P0_MAP1_DMA_PL230_R0P0_ALL_SOFTREQ_TABLE.

Return to the Summary Table.

Channel Software Request

Figure 15-12 SOFTREQ Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CHNLS
W-0h
Table 15-14 SOFTREQ Register Field Descriptions
Bit Field Type Reset Description
31-0 CHNLS W 0h Set the appropriate bit to generate a software uDMA request on the corresponding uDMA channel
Bit [Ch] = 0: Does not create a uDMA request for channel Ch
Bit [Ch] = 1: Creates a uDMA request for channel Ch
Writing to a bit where a uDMA channel is not implemented does not create a uDMA request for that channel

15.5.1.7 SETBURST Register (Offset = 18h) [Reset = 00000000h]

SETBURST is shown in #DMA_PL230_R0P0_DMA_PL230_R0P0_MAP1_DMA_PL230_R0P0_ALL_SETBURST_FIGURE and described in #DMA_PL230_R0P0_DMA_PL230_R0P0_MAP1_DMA_PL230_R0P0_ALL_SETBURST_TABLE.

Return to the Summary Table.

Channel Set UseBurst

Figure 15-13 SETBURST Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CHNLS
R/W-0h
Table 15-15 SETBURST Register Field Descriptions
Bit Field Type Reset Description
31-0 CHNLS R/W 0h Returns the useburst status, or disables individual channels from generating single uDMA requests. The value R is the arbitration rate and stored in the controller data structure.
Read as:
Bit [Ch] = 0: uDMA channel Ch responds to both burst and single requests on channel C. The controller performs 2R, or single, bus transfers.
Bit [Ch] = 1: uDMA channel Ch does not respond to single transfer requests. The controller only responds to burst transfer requests and performs 2R transfers.
Write as:
Bit [Ch] = 0: No effect. Use the CLEARBURST.CHNLS to set bit [Ch] to 0.
Bit [Ch] = 1: Disables single transfer requests on channel Ch. The controller performs 2R transfers for burst requests.
Writing to a bit where a uDMA channel is not implemented has no effect

15.5.1.8 CLEARBURST Register (Offset = 1Ch) [Reset = 00000000h]

CLEARBURST is shown in #DMA_PL230_R0P0_DMA_PL230_R0P0_MAP1_DMA_PL230_R0P0_ALL_CLEARBURST_FIGURE and described in #DMA_PL230_R0P0_DMA_PL230_R0P0_MAP1_DMA_PL230_R0P0_ALL_CLEARBURST_TABLE.

Return to the Summary Table.

Channel Clear UseBurst

Figure 15-14 CLEARBURST Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CHNLS
W-0h
Table 15-16 CLEARBURST Register Field Descriptions
Bit Field Type Reset Description
31-0 CHNLS W 0h Set the appropriate bit to enable single transfer requests.
Write as:
Bit [Ch] = 0: No effect. Use the SETBURST.CHNLS to disable single transfer requests.
Bit [Ch] = 1: Enables single transfer requests on channel Ch.
Writing to a bit where a DMA channel is not implemented has no effect.

15.5.1.9 SETREQMASK Register (Offset = 20h) [Reset = 00000000h]

SETREQMASK is shown in #DMA_PL230_R0P0_DMA_PL230_R0P0_MAP1_DMA_PL230_R0P0_ALL_SETREQMASK_FIGURE and described in #DMA_PL230_R0P0_DMA_PL230_R0P0_MAP1_DMA_PL230_R0P0_ALL_SETREQMASK_TABLE.

Return to the Summary Table.

Channel Set Request Mask

Figure 15-15 SETREQMASK Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CHNLS
R/W-0h
Table 15-17 SETREQMASK Register Field Descriptions
Bit Field Type Reset Description
31-0 CHNLS R/W 0h Returns the burst and single request mask status, or disables the corresponding channel from generating uDMA requests.
Read as:
Bit [Ch] = 0: External requests are enabled for channel Ch.
Bit [Ch] = 1: External requests are disabled for channel Ch.
Write as:
Bit [Ch] = 0: No effect. Use the CLEARREQMASK.CHNLS to enable uDMA requests.
Bit [Ch] = 1: Disables uDMA burst request channel [C] and uDMA single request channel [C] input from generating uDMA requests.
Writing to a bit where a uDMA channel is not implemented has no effect

15.5.1.10 CLEARREQMASK Register (Offset = 24h) [Reset = 00000000h]

CLEARREQMASK is shown in #DMA_PL230_R0P0_DMA_PL230_R0P0_MAP1_DMA_PL230_R0P0_ALL_CLEARREQMASK_FIGURE and described in #DMA_PL230_R0P0_DMA_PL230_R0P0_MAP1_DMA_PL230_R0P0_ALL_CLEARREQMASK_TABLE.

Return to the Summary Table.

Clear Channel Request Mask

Figure 15-16 CLEARREQMASK Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CHNLS
W-0h
Table 15-18 CLEARREQMASK Register Field Descriptions
Bit Field Type Reset Description
31-0 CHNLS W 0h Set the appropriate bit to enable DMA request for the channel.
Write as:
Bit [Ch] = 0: No effect. Use the SETREQMASK.CHNLS to disable channel C from generating requests.
Bit [Ch] = 1: Enables channel [C] to generate DMA requests.
Writing to a bit where a DMA channel is not implemented has no effect.

15.5.1.11 SETCHANNELEN Register (Offset = 28h) [Reset = 00000000h]

SETCHANNELEN is shown in #DMA_PL230_R0P0_DMA_PL230_R0P0_MAP1_DMA_PL230_R0P0_ALL_SETCHANNELEN_FIGURE and described in #DMA_PL230_R0P0_DMA_PL230_R0P0_MAP1_DMA_PL230_R0P0_ALL_SETCHANNELEN_TABLE.

Return to the Summary Table.

Set Channel Enable

Figure 15-17 SETCHANNELEN Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CHNLS
R/W-0h
Table 15-19 SETCHANNELEN Register Field Descriptions
Bit Field Type Reset Description
31-0 CHNLS R/W 0h Returns the enable status of the channels, or enables the corresponding channels.
Read as:
Bit [Ch] = 0: Channel Ch is disabled.
Bit [Ch] = 1: Channel Ch is enabled.
Write as:
Bit [Ch] = 0: No effect. Use the CLEARCHANNELEN.CHNLS to disable a channel
Bit [Ch] = 1: Enables channel Ch
Writing to a bit where a DMA channel is not implemented has no effect

15.5.1.12 CLEARCHANNELEN Register (Offset = 2Ch) [Reset = 00000000h]

CLEARCHANNELEN is shown in #DMA_PL230_R0P0_DMA_PL230_R0P0_MAP1_DMA_PL230_R0P0_ALL_CLEARCHANNELEN_FIGURE and described in #DMA_PL230_R0P0_DMA_PL230_R0P0_MAP1_DMA_PL230_R0P0_ALL_CLEARCHANNELEN_TABLE.

Return to the Summary Table.

Clear Channel Enable

Figure 15-18 CLEARCHANNELEN Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CHNLS
W-0h
Table 15-20 CLEARCHANNELEN Register Field Descriptions
Bit Field Type Reset Description
31-0 CHNLS W 0h Set the appropriate bit to disable the corresponding uDMA channel.
Write as:
Bit [Ch] = 0: No effect. Use the SETCHANNELEN.CHNLS to enable uDMA channels.
Bit [Ch] = 1: Disables channel Ch
Writing to a bit where a uDMA channel is not implemented has no effect

15.5.1.13 SETCHNLPRIALT Register (Offset = 30h) [Reset = 00000000h]

SETCHNLPRIALT is shown in #DMA_PL230_R0P0_DMA_PL230_R0P0_MAP1_DMA_PL230_R0P0_ALL_SETCHNLPRIALT_FIGURE and described in #DMA_PL230_R0P0_DMA_PL230_R0P0_MAP1_DMA_PL230_R0P0_ALL_SETCHNLPRIALT_TABLE.

Return to the Summary Table.

Channel Set Primary-Alternate

Figure 15-19 SETCHNLPRIALT Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CHNLS
R/W-0h
Table 15-21 SETCHNLPRIALT Register Field Descriptions
Bit Field Type Reset Description
31-0 CHNLS R/W 0h Returns the channel control data structure status, or selects the alternate data structure for the corresponding uDMA channel.
Read as:
Bit [Ch] = 0: uDMA channel Ch is using the primary data structure.
Bit [Ch] = 1: uDMA channel Ch is using the alternate data structure.
Write as:
Bit [Ch] = 0: No effect. Use the CLEARCHNLPRIALT.CHNLS to disable a channel
Bit [Ch] = 1: Selects the alternate data structure for channel Ch
Writing to a bit where a uDMA channel is not implemented has no effect

15.5.1.14 CLEARCHNLPRIALT Register (Offset = 34h) [Reset = 00000000h]

CLEARCHNLPRIALT is shown in #DMA_PL230_R0P0_DMA_PL230_R0P0_MAP1_DMA_PL230_R0P0_ALL_CLEARCHNLPRIALT_FIGURE and described in #DMA_PL230_R0P0_DMA_PL230_R0P0_MAP1_DMA_PL230_R0P0_ALL_CLEARCHNLPRIALT_TABLE.

Return to the Summary Table.

Channel Clear Primary-Alternate

Figure 15-20 CLEARCHNLPRIALT Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CHNLS
W-0h
Table 15-22 CLEARCHNLPRIALT Register Field Descriptions
Bit Field Type Reset Description
31-0 CHNLS W 0h Clears the appropriate bit to select the primary data structure for the corresponding uDMA channel.
Write as:
Bit [Ch] = 0: No effect. Use the SETCHNLPRIALT.CHNLS to select the alternate data structure.
Bit [Ch] = 1: Selects the primary data structure for channel Ch.
Writing to a bit where a uDMA channel is not implemented has no effect

15.5.1.15 SETCHNLPRIORITY Register (Offset = 38h) [Reset = 00000000h]

SETCHNLPRIORITY is shown in #DMA_PL230_R0P0_DMA_PL230_R0P0_MAP1_DMA_PL230_R0P0_ALL_SETCHNLPRIORITY_FIGURE and described in #DMA_PL230_R0P0_DMA_PL230_R0P0_MAP1_DMA_PL230_R0P0_ALL_SETCHNLPRIORITY_TABLE.

Return to the Summary Table.

Set Channel Priority

Figure 15-21 SETCHNLPRIORITY Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CHNLS
R/W-0h
Table 15-23 SETCHNLPRIORITY Register Field Descriptions
Bit Field Type Reset Description
31-0 CHNLS R/W 0h Returns the channel priority mask status, or sets the channel priority to high.
Read as:
Bit [Ch] = 0: uDMA channel Ch is using the default priority level.
Bit [Ch] = 1: uDMA channel Ch is using a high priority level.
Write as:
Bit [Ch] = 0: No effect. Use the CLEARCHNLPRIORITY.CHNLS to set channel Ch to the default priority level.
Bit [Ch] = 1: Channel Ch uses the high priority level.
Writing to a bit where a uDMA channel is not implemented has no effect

15.5.1.16 CLEARCHNLPRIORITY Register (Offset = 3Ch) [Reset = 00000000h]

CLEARCHNLPRIORITY is shown in #DMA_PL230_R0P0_DMA_PL230_R0P0_MAP1_DMA_PL230_R0P0_ALL_CLEARCHNLPRIORITY_FIGURE and described in #DMA_PL230_R0P0_DMA_PL230_R0P0_MAP1_DMA_PL230_R0P0_ALL_CLEARCHNLPRIORITY_TABLE.

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Clear Channel Priority

Figure 15-22 CLEARCHNLPRIORITY Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CHNLS
W-0h
Table 15-24 CLEARCHNLPRIORITY Register Field Descriptions
Bit Field Type Reset Description
31-0 CHNLS W 0h Clear the appropriate bit to select the default priority level for the specified uDMA channel.
Write as:
Bit [Ch] = 0: No effect. Use the SETCHNLPRIORITY.CHNLS to set channel Ch to the high priority level.
Bit [Ch] = 1: Channel Ch uses the default priority level.
Writing to a bit where a uDMA channel is not implemented has no effect

15.5.1.17 ERROR Register (Offset = 4Ch) [Reset = 00000000h]

ERROR is shown in #DMA_PL230_R0P0_DMA_PL230_R0P0_MAP1_DMA_PL230_R0P0_ALL_ERROR_FIGURE and described in #DMA_PL230_R0P0_DMA_PL230_R0P0_MAP1_DMA_PL230_R0P0_ALL_ERROR_TABLE.

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Error Status and Clear

Figure 15-23 ERROR Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED STATUS
R-0h R/W-0h
Table 15-25 ERROR Register Field Descriptions
Bit Field Type Reset Description
31-1 RESERVED R 0h Reserved
0 STATUS R/W 0h Returns the status of bus error flag in uDMA, or clears this bit
Read as:
0: No bus error detected
1: Bus error detected
Write as:
0: No effect, status of bus error flag is unchanged.
1: Clears the bus error flag.

15.5.1.18 REQDONE Register (Offset = 504h) [Reset = 00000000h]

REQDONE is shown in #DMA_PL230_R0P0_DMA_PL230_R0P0_MAP1_DMA_PL230_R0P0_ALL_REQDONE_FIGURE and described in #DMA_PL230_R0P0_DMA_PL230_R0P0_MAP1_DMA_PL230_R0P0_ALL_REQDONE_TABLE.

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Channel Request Done

Figure 15-24 REQDONE Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CHNLS
R/W-0h
Table 15-26 REQDONE Register Field Descriptions
Bit Field Type Reset Description
31-0 CHNLS R/W 0h Reflects the uDMA done status for the given channel, channel [Ch]. It's a sticky done bit. Unless cleared by writing a 1, it holds the value of 1.
Read as:
Bit [Ch] = 0: Request has not completed for channel Ch
Bit [Ch] = 1: Request has completed for the channel Ch
Writing a 1 to individual bits would clear the corresponding bit.
Write as:
Bit [Ch] = 0: No effect.
Bit [Ch] = 1: The corresponding [Ch] bit is cleared and is set to 0

15.5.1.19 DONEMASK Register (Offset = 520h) [Reset = 00000000h]

DONEMASK is shown in #DMA_PL230_R0P0_DMA_PL230_R0P0_MAP1_DMA_PL230_R0P0_ALL_DONEMASK_FIGURE and described in #DMA_PL230_R0P0_DMA_PL230_R0P0_MAP1_DMA_PL230_R0P0_ALL_DONEMASK_TABLE.

Return to the Summary Table.

Channel Request Done Mask

Figure 15-25 DONEMASK Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CHNLS
R/W-0h
Table 15-27 DONEMASK Register Field Descriptions
Bit Field Type Reset Description
31-0 CHNLS R/W 0h Controls the propagation of the uDMA done and active state to the assigned peripheral. Specifically used for software channels.
Read as:
Bit [Ch] = 0: uDMA done and active state for channel Ch is not blocked from reaching to the peripherals.
Note that the uDMA done state for channel [Ch] is blocked from contributing to generation of combined uDMA done signal
Bit [Ch] = 1: uDMA done and active state for channel Ch is blocked from reaching to the peripherals.
Note that the uDMA done state for channel [Ch] is not blocked from contributing to generation of combined uDMA done signal
Write as:
Bit [Ch] = 0: Allows uDMA done and active stat to propagate to the peripherals.
Note that this disables uDMA done state for channel [Ch] from contributing to generation of combined uDMA done signal
Bit [Ch] = 1: Blocks uDMA done and active state to propagate to the peripherals.
Note that this enables uDMA done for channel [Ch] to contribute to generation of combined uDMA done signal.