SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7
#RFCORE_IG_RAT_RFCORE_IG_RAT_MAP_RAT_TABLE_1 lists the memory-mapped registers for the RFC_RAT registers. All register offset addresses not listed in #RFCORE_IG_RAT_RFCORE_IG_RAT_MAP_RAT_TABLE_1 should be considered as reserved locations and the register contents should not be modified.
Complex bit access types are encoded to fit into small table cells. #RFCORE_IG_RAT_RFCORE_IG_RAT_MAP_RAT_LEGEND shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Write Type | ||
W | W | Write |
Reset or Default Value | ||
-n | Value after reset or the default value |
RATCNT is shown in #RFCORE_IG_RAT_RFCORE_IG_RAT_MAP_RAT_RFCORE_IG_RAT_ALL_RATCNT_FIGURE and described in #RFCORE_IG_RAT_RFCORE_IG_RAT_MAP_RAT_RFCORE_IG_RAT_ALL_RATCNT_TABLE.
Return to the Summary Table.
Radio Timer Counter Value
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CNT | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | CNT | R/W | 0h | Counter value. This is not writable while radio timer counter is enabled. |
RATCH0VAL is shown in #RFCORE_IG_RAT_RFCORE_IG_RAT_MAP_RAT_RFCORE_IG_RAT_ALL_RATCH0VAL_FIGURE and described in #RFCORE_IG_RAT_RFCORE_IG_RAT_MAP_RAT_RFCORE_IG_RAT_ALL_RATCH0VAL_TABLE.
Return to the Summary Table.
Timer Channel 0 Capture/Compare Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VAL | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VAL | R/W | 0h | Capture/compare value. Only writable when the channel is configured for compare mode. In compare mode, a write to this register will auto-arm the channel. |
RATCH1VAL is shown in #RFCORE_IG_RAT_RFCORE_IG_RAT_MAP_RAT_RFCORE_IG_RAT_ALL_RATCH1VAL_FIGURE and described in #RFCORE_IG_RAT_RFCORE_IG_RAT_MAP_RAT_RFCORE_IG_RAT_ALL_RATCH1VAL_TABLE.
Return to the Summary Table.
Timer Channel 1 Capture/Compare Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VAL | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VAL | R/W | 0h | Capture/compare value. Only writable when the channel is configured for compare mode. In compare mode, a write to this register will auto-arm the channel. |
RATCH2VAL is shown in #RFCORE_IG_RAT_RFCORE_IG_RAT_MAP_RAT_RFCORE_IG_RAT_ALL_RATCH2VAL_FIGURE and described in #RFCORE_IG_RAT_RFCORE_IG_RAT_MAP_RAT_RFCORE_IG_RAT_ALL_RATCH2VAL_TABLE.
Return to the Summary Table.
Timer Channel 2 Capture/Compare Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VAL | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VAL | R/W | 0h | Capture/compare value. Only writable when the channel is configured for compare mode. In compare mode, a write to this register will auto-arm the channel. |
RATCH3VAL is shown in #RFCORE_IG_RAT_RFCORE_IG_RAT_MAP_RAT_RFCORE_IG_RAT_ALL_RATCH3VAL_FIGURE and described in #RFCORE_IG_RAT_RFCORE_IG_RAT_MAP_RAT_RFCORE_IG_RAT_ALL_RATCH3VAL_TABLE.
Return to the Summary Table.
Timer Channel 3 Capture/Compare Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VAL | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VAL | R/W | 0h | Capture/compare value. Only writable when the channel is configured for compare mode. In compare mode, a write to this register will auto-arm the channel. |
RATCH4VAL is shown in #RFCORE_IG_RAT_RFCORE_IG_RAT_MAP_RAT_RFCORE_IG_RAT_ALL_RATCH4VAL_FIGURE and described in #RFCORE_IG_RAT_RFCORE_IG_RAT_MAP_RAT_RFCORE_IG_RAT_ALL_RATCH4VAL_TABLE.
Return to the Summary Table.
Timer Channel 4 Capture/Compare Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VAL | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VAL | R/W | 0h | Capture/compare value. Only writable when the channel is configured for compare mode. In compare mode, a write to this register will auto-arm the channel. |
RATCH5VAL is shown in #RFCORE_IG_RAT_RFCORE_IG_RAT_MAP_RAT_RFCORE_IG_RAT_ALL_RATCH5VAL_FIGURE and described in #RFCORE_IG_RAT_RFCORE_IG_RAT_MAP_RAT_RFCORE_IG_RAT_ALL_RATCH5VAL_TABLE.
Return to the Summary Table.
Timer Channel 5 Capture/Compare Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VAL | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VAL | R/W | 0h | Capture/compare value. Only writable when the channel is configured for compare mode. In compare mode, a write to this register will auto-arm the channel. |
RATCH6VAL is shown in #RFCORE_IG_RAT_RFCORE_IG_RAT_MAP_RAT_RFCORE_IG_RAT_ALL_RATCH6VAL_FIGURE and described in #RFCORE_IG_RAT_RFCORE_IG_RAT_MAP_RAT_RFCORE_IG_RAT_ALL_RATCH6VAL_TABLE.
Return to the Summary Table.
Timer Channel 6 Capture/Compare Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VAL | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VAL | R/W | 0h | Capture/compare value. Only writable when the channel is configured for compare mode. In compare mode, a write to this register will auto-arm the channel. |
RATCH7VAL is shown in #RFCORE_IG_RAT_RFCORE_IG_RAT_MAP_RAT_RFCORE_IG_RAT_ALL_RATCH7VAL_FIGURE and described in #RFCORE_IG_RAT_RFCORE_IG_RAT_MAP_RAT_RFCORE_IG_RAT_ALL_RATCH7VAL_TABLE.
Return to the Summary Table.
Timer Channel 7 Capture/Compare Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VAL | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VAL | R/W | 0h | Capture/compare value. Only writable when the channel is configured for compare mode. In compare mode, a write to this register will auto-arm the channel. |