SWCU192 November   2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7

 

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    9.     402
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  14.   404
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    4.     448
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    5.     454
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  16.   456
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    3.     459
      1.      460
      2.      461
        1.       462
        2.       463
        3.       464
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        5.       466
      3.      467
      4.      468
    4.     469
      1.      470
      2.      471
      3.      472
      4.      473
      5.      474
    5.     475
      1.      476
  17.   477
    1.     478
    2.     479
      1.      480
      2.      481
      3.      482
        1.       483
      4.      484
    3.     485
      1.      486
      2.      487
      3.      488
    4.     489
      1.      490
  18.   491
    1.     492
    2.     493
    3.     494
    4.     495
      1.      496
  19.   497
    1.     498
    2.     499
    3.     500
    4.     501
    5.     502
      1.      503
      2.      504
      3.      505
    6.     506
      1.      507
        1.       508
        2.       509
        3.       510
          1.        511
          2.        512
    7.     513
      1.      514
  20.   515
    1.     516
      1.      517
    2.     518
      1.      519
        1.       520
      2.      521
        1.       522
        2.       523
      3.      524
      4.      525
    3.     526
      1.      527
        1.       528
        2.       529
        3.       530
        4.       531
      2.      532
        1.       533
          1.        534
        2.       535
          1.        536
          2.        537
        3.       538
          1.        539
        4.       540
          1.        541
          2.        542
          3.        543
        5.       544
        6.       545
        7.       546
        8.       547
        9.       548
        10.       549
    4.     550
      1.      551
        1.       552
      2.      553
        1.       554
        2.       555
          1.        556
          2.        557
          3.        558
          4.        559
          5.        560
      3.      561
        1.       562
        2.       563
        3.       564
      4.      565
        1.       566
        2.       567
          1.        568
          2.        569
          3.        570
      5.      571
        1.       572
        2.       573
          1.        574
          2.        575
          3.        576
          4.        577
            1.         578
            2.         579
          5.        580
          6.        581
        3.       582
          1.        583
          2.        584
          3.        585
            1.         586
            2.         587
            3.         588
            4.         589
          4.        590
      6.      591
        1.       592
        2.       593
      7.      594
        1.       595
        2.       596
          1.        597
          2.        598
          3.        599
          4.        600
          5.        601
            1.         602
              1.          603
            2.         604
              1.          605
            3.         606
              1.          607
          6.        608
    5.     609
      1.      610
        1.       611
        2.       612
      2.      613
        1.       614
        2.       615
          1.        616
          2.        617
          3.        618
          4.        619
          5.        620
          6.        621
          7.        622
          8.        623
      3.      624
        1.       625
        2.       626
          1.        627
          2.        628
          3.        629
          4.        630
      4.      631
        1.       632
        2.       633
          1.        634
          2.        635
          3.        636
            1.         637
            2.         638
      5.      639
        1.       640
        2.       641
          1.        642
          2.        643
          3.        644
            1.         645
            2.         646
            3.         647
          4.        648
            1.         649
            2.         650
            3.         651
            4.         652
          5.        653
          6.        654
      6.      655
        1.       656
        2.       657
          1.        658
          2.        659
          3.        660
          4.        661
          5.        662
    6.     663
      1.      664
        1.       665
        2.       666
          1.        667
            1.         668
            2.         669
      2.      670
      3.      671
      4.      672
      5.      673
      6.      674
      7.      675
    7.     676
    8.     677
      1.      678
      2.      679
      3.      680
      4.      681
      5.      682
      6.      683
      7.      684
      8.      685
      9.      686
      10.      687
      11.      688
      12.      689
  21.   690
    1.     691
    2.     692
    3.     693
      1.      694
  22.   695
    1.     696
    2.     697
    3.     698
    4.     699
      1.      700
      2.      701
      3.      702
      4.      703
        1.       704
        2.       705
          1.        706
          2.        707
      5.      708
      6.      709
      7.      710
    5.     711
    6.     712
    7.     713
      1.      714
  23.   715
    1.     716
    2.     717
    3.     718
    4.     719
      1.      720
      2.      721
        1.       722
        2.       723
      3.      724
      4.      725
        1.       726
        2.       727
          1.        728
          2.        729
        3.       730
        4.       731
        5.       732
        6.       733
        7.       734
    5.     735
    6.     736
    7.     737
      1.      738
  24.   739
    1.     740
    2.     741
    3.     742
      1.      743
        1.       744
        2.       745
        3.       746
        4.       747
        5.       748
      2.      749
        1.       750
      3.      751
        1.       752
        2.       753
      4.      754
      5.      755
        1.       756
        2.       757
    4.     758
    5.     759
      1.      760
  25.   761
    1.     762
    2.     763
    3.     764
    4.     765
      1.      766
        1.       767
      2.      768
      3.      769
      4.      770
        1.       771
      5.      772
        1.       773
      6.      774
        1.       775
      7.      776
        1.       777
      8.      778
        1.       779
        2.       780
    5.     781
      1.      782
      2.      783
      3.      784
      4.      785
        1.       786
        2.       787
        3.       788
    6.     789
      1.      790
      2.      791
      3.      792
      4.      793
    7.     794
    8.     795
      1.      796
      2.      797
    9.     798
      1.      799
  26.   800
    1.     801
      1.      802
    2.     803
      1.      804
      2.      805
      3.      806
        1.       807
        2.       808
        3.       809
      4.      810
        1.       811
        2.       812
        3.       813
    3.     814
      1.      815
      2.      816
        1.       817
        2.       818
        3.       819
        4.       820
        5.       821
          1.        822
          2.        823
          3.        824
        6.       825
          1.        826
        7.       827
          1.        828
          2.        829
          3.        830
          4.        831
        8.       832
      3.      833
        1.       834
          1.        835
          2.        836
          3.        837
          4.        838
          5.        839
          6.        840
          7.        841
          8.        842
          9.        843
          10.        844
          11.        845
          12.        846
          13.        847
          14.        848
        2.       849
          1.        850
          2.        851
          3.        852
          4.        853
          5.        854
          6.        855
          7.        856
          8.        857
          9.        858
          10.        859
          11.        860
          12.        861
          13.        862
          14.        863
          15.        864
          16.        865
          17.        866
          18.        867
          19.        868
          20.        869
      4.      870
        1.       871
        2.       872
        3.       873
        4.       874
        5.       875
    4.     876
      1.      877
        1.       878
        2.       879
        3.       880
        4.       881
        5.       882
      2.      883
        1.       884
        2.       885
    5.     886
      1.      887
        1.       888
        2.       889
        3.       890
        4.       891
      2.      892
      3.      893
        1.       894
        2.       895
      4.      896
        1.       897
          1.        898
            1.         899
            2.         900
          2.        901
          3.        902
          4.        903
          5.        904
        2.       905
        3.       906
        4.       907
        5.       908
        6.       909
      5.      910
        1.       911
        2.       912
        3.       913
        4.       914
        5.       915
        6.       916
    6.     917
      1.      918
        1.       919
          1.        920
        2.       921
        3.       922
        4.       923
      2.      924
    7.     925
      1.      926
      2.      927
    8.     928
      1.      929
      2.      930
      3.      931
      4.      932
      5.      933
      6.      934
      7.      935
      8.      936
        1.       937
        2.       938
        3.       939
        4.       940
      9.      941
        1.       942
        2.       943
        3.       944
      10.      945
        1.       946
        2.       947
        3.       948
        4.       949
        5.       950
      11.      951
        1.       952
        2.       953
        3.       954
        4.       955
        5.       956
      12.      957
      13.      958
      14.      959
      15.      960
      16.      961
      17.      962
    9.     963
      1.      964
    10.     965
      1.      966
      2.      967
        1.       968
          1.        969
        2.       970
        3.       971
      3.      972
      4.      973
        1.       974
        2.       975
      5.      976
        1.       977
        2.       978
          1.        979
        3.       980
          1.        981
          2.        982
        4.       983
          1.        984
          2.        985
        5.       986
          1.        987
          2.        988
          3.        989
      6.      990
        1.       991
        2.       992
    11.     993
      1.      994
      2.      995
      3.      996
  27.   997

AON_PMCTL Registers

#AON_PMCTRL_AON_PMCTRL_AON_PMCTRL_REGMAP_TABLE_1 lists the memory-mapped registers for the AON_PMCTL registers. All register offset addresses not listed in #AON_PMCTRL_AON_PMCTRL_AON_PMCTRL_REGMAP_TABLE_1 should be considered as reserved locations and the register contents should not be modified.

Complex bit access types are encoded to fit into small table cells. #AON_PMCTRL_AON_PMCTRL_AON_PMCTRL_REGMAP_LEGEND shows the codes that are used for access types in this section.

Table 8-100 AON_PMCTL Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
W1CW
1C
Write
1 to clear
Reset or Default Value
-nValue after reset or the default value

8.8.3.1 AUXSCECLK Register (Offset = 4h) [Reset = 00000000h]

AUXSCECLK is shown in #AON_PMCTRL_AON_PMCTRL_AON_PMCTRL_REGMAP_AON_PMCTRL_ALL_AUXSCECLK_FIGURE and described in #AON_PMCTRL_AON_PMCTRL_AON_PMCTRL_REGMAP_AON_PMCTRL_ALL_AUXSCECLK_TABLE.

Return to the Summary Table.

AUX SCE Clock Management
This register contains bitfields that are relevant for setting up the clock to the AUX domain.

Figure 8-94 AUXSCECLK Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDPD_SRC
R-0hR/W-0h
76543210
RESERVEDSRC
R-0hR/W-0h
Table 8-101 AUXSCECLK Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0hReserved
8PD_SRCR/W0hSelects the clock source for the AUX domain when AUX is in powerdown mode.
Note: Switching the clock source is guaranteed to be glitch-free

0h = No clock

1h = LF clock (SCLK_LF )

7-1RESERVEDR0hReserved
0SRCR/W0hSelects the clock source for the AUX domain when AUX is in active mode.
Note: Switching the clock source is guaranteed to be glitch-free

0h = HF Clock divided by 2 (SCLK_HFDIV2)

1h = MF Clock (SCLK_MF)

8.8.3.2 RAMCFG Register (Offset = 8h) [Reset = 0001000Fh]

RAMCFG is shown in #AON_PMCTRL_AON_PMCTRL_AON_PMCTRL_REGMAP_AON_PMCTRL_ALL_RAMCFG_FIGURE and described in #AON_PMCTRL_AON_PMCTRL_AON_PMCTRL_REGMAP_AON_PMCTRL_ALL_RAMCFG_TABLE.

Return to the Summary Table.

RAM Configuration
This register contains power management related configuration for the SRAM in the MCU and AUX domain.

Figure 8-95 RAMCFG Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDAUX_SRAM_PWR_OFFAUX_SRAM_RET_EN
R-0hR/W-0hR/W-1h
15141312111098
RESERVED
R-0h
76543210
RESERVEDBUS_SRAM_RET_EN
R-0hR/W-Fh
Table 8-102 RAMCFG Register Field Descriptions
BitFieldTypeResetDescription
31-18RESERVEDR0hReserved
17AUX_SRAM_PWR_OFFR/W0hInternal. Only to be used through TI provided API.
16AUX_SRAM_RET_ENR/W1hInternal. Only to be used through TI provided API.
15-4RESERVEDR0hReserved
3-0BUS_SRAM_RET_ENR/WFhMCU SRAM is partitioned into 5 banks . This register controls which of the banks that has retention during MCU Bus domain power off

0h = Retention is disabled

3h = Retention on for SRAM:BANK0, SRAM:BANK1 and SRAM:BANK2

7h = Retention on for SRAM:BANK0, SRAM:BANK1 ,SRAM:BANK2 and SRAM:BANK3

Fh = Retention on for all banks SRAM:BANK0, SRAM:BANK1 ,SRAM:BANK2, SRAM:BANK3 and SRAM:BANK4

8.8.3.3 PWRCTL Register (Offset = 10h) [Reset = 00000000h]

PWRCTL is shown in #AON_PMCTRL_AON_PMCTRL_AON_PMCTRL_REGMAP_AON_PMCTRL_ALL_PWRCTL_FIGURE and described in #AON_PMCTRL_AON_PMCTRL_AON_PMCTRL_REGMAP_AON_PMCTRL_ALL_PWRCTL_TABLE.

Return to the Summary Table.

Power Management Control
This register controls bitfields for setting low level power management features such as selection of regulator for VDDR supply and control of IO ring where certain segments can be enabled / disabled.

Figure 8-96 PWRCTL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDDCDC_ACTIVEEXT_REG_MODEDCDC_EN
R-0hR/W-0hR-0hR/W-0h
Table 8-103 PWRCTL Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0hReserved
2DCDC_ACTIVER/W0hSelect to use DCDC regulator for VDDR in active mode
0: Use GLDO for regulation of VDDR in active mode.
1: Use DCDC for regulation of VDDR in active mode.
DCDC_EN must also be set for DCDC to be used as regulator for VDDR in active mode
1EXT_REG_MODER0hStatus of source for VDDRsupply:
0: DCDC or GLDO are generating VDDR
1: DCDC and GLDO are bypassed and an external regulator supplies VDDR
0DCDC_ENR/W0hSelect to use DCDC regulator during recharge of VDDR
0: Use GLDO for recharge of VDDR
1: Use DCDC for recharge of VDDR
Note: This bitfield should be set to the same as DCDC_ACTIVE

8.8.3.4 PWRSTAT Register (Offset = 14h) [Reset = 03C00003h]

PWRSTAT is shown in #AON_PMCTRL_AON_PMCTRL_AON_PMCTRL_REGMAP_AON_PMCTRL_ALL_PWRSTAT_FIGURE and described in #AON_PMCTRL_AON_PMCTRL_AON_PMCTRL_REGMAP_AON_PMCTRL_ALL_PWRSTAT_TABLE.

Return to the Summary Table.

AON Power and Reset Status
This register is used to monitor various power management related signals in AON. All other signals than JTAG_PD_ON, AUX_BUS_RESET_DONE, and AUX_RESET_DONE are for test, calibration and debug purpose only.

Figure 8-97 PWRSTAT Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDJTAG_PD_ONAUX_BUS_RESET_DONEAUX_RESET_DONE
R-0hR-0hR-1hR-1h
Table 8-104 PWRSTAT Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0hReserved
2JTAG_PD_ONR0hIndicates JTAG power state:
0: JTAG is powered off
1: JTAG is powered on
1AUX_BUS_RESET_DONER1hIndicates Reset Done from AUX Bus:
0: AUX Bus is being reset
1: AUX Bus reset is released
0AUX_RESET_DONER1hIndicates Reset Done from AUX:
0: AUX is being reset
1: AUX reset is released

8.8.3.5 SHUTDOWN Register (Offset = 18h) [Reset = 00000000h]

SHUTDOWN is shown in #AON_PMCTRL_AON_PMCTRL_AON_PMCTRL_REGMAP_AON_PMCTRL_ALL_SHUTDOWN_FIGURE and described in #AON_PMCTRL_AON_PMCTRL_AON_PMCTRL_REGMAP_AON_PMCTRL_ALL_SHUTDOWN_TABLE.

Return to the Summary Table.

Shutdown Control
This register contains bitfields required for entering shutdown mode

Figure 8-98 SHUTDOWN Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDEN
R-0hR/W-0h
Table 8-105 SHUTDOWN Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0ENR/W0hShutdown control.
0: Do not write 0 to this bit.
1: Immediately start the process to enter shutdown mode

8.8.3.6 RECHARGECFG Register (Offset = 1Ch) [Reset = C0000000h]

RECHARGECFG is shown in #AON_PMCTRL_AON_PMCTRL_AON_PMCTRL_REGMAP_AON_PMCTRL_ALL_RECHARGECFG_FIGURE and described in #AON_PMCTRL_AON_PMCTRL_AON_PMCTRL_REGMAP_AON_PMCTRL_ALL_RECHARGECFG_TABLE.

Return to the Summary Table.

Recharge Controller Configuration
This register sets all relevant parameters for controlling the recharge algorithm.

Figure 8-99 RECHARGECFG Register
31302928272625242322212019181716
MODERESERVEDC2C1
R/W-3hR-0hR/W-0hR/W-0h
1514131211109876543210
MAX_PER_MMAX_PER_EPER_MPER_E
R/W-0hR/W-0hR/W-0hR/W-0h
Table 8-106 RECHARGECFG Register Field Descriptions
BitFieldTypeResetDescription
31-30MODER/W3hSelects recharge algorithm for VDDR when the system is running on the uLDO

0h = Recharge disabled

1h = Static timer

2h = Adaptive timer

3h = External recharge comparator.
Note that the clock to the recharge comparator must be enabled, [ANATOP_MMAP:ADI_3_REFSYS:CTL_RECHARGE_CMP0:COMP_CLK_DISABLE], before selecting this recharge algorithm.

29-24RESERVEDR0hReserved
23-20C2R/W0hInternal. Only to be used through TI provided API.
19-16C1R/W0hInternal. Only to be used through TI provided API.
15-11MAX_PER_MR/W0hInternal. Only to be used through TI provided API.
10-8MAX_PER_ER/W0hInternal. Only to be used through TI provided API.
7-3PER_MR/W0hInternal. Only to be used through TI provided API.
2-0PER_ER/W0hInternal. Only to be used through TI provided API.

8.8.3.7 RECHARGESTAT Register (Offset = 20h) [Reset = 00000000h]

RECHARGESTAT is shown in #AON_PMCTRL_AON_PMCTRL_AON_PMCTRL_REGMAP_AON_PMCTRL_ALL_RECHARGESTAT_FIGURE and described in #AON_PMCTRL_AON_PMCTRL_AON_PMCTRL_REGMAP_AON_PMCTRL_ALL_RECHARGESTAT_TABLE.

Return to the Summary Table.

Recharge Controller Status
This register controls various status registers which are updated during recharge. The register is mostly intended for test and debug.

Figure 8-100 RECHARGESTAT Register
31302928272625242322212019181716
RESERVEDVDDR_SMPLS
R-0hR-0h
1514131211109876543210
MAX_USED_PER
R/W-0h
Table 8-107 RECHARGESTAT Register Field Descriptions
BitFieldTypeResetDescription
31-20RESERVEDR0hReserved
19-16VDDR_SMPLSR0hThe last 4 VDDR samples.
For each bit:
0: VDDR was below VDDR_OK threshold when recharge started
1: VDDR was above VDDR_OK threshold when recharge started
The register is updated prior to every recharge period with a shift left, and bit 0 is updated with the last VDDR sample.
15-0MAX_USED_PERR/W0hShows the maximum number of 32kHz periods that have separated two recharge cycles and VDDR still was above VDDR_OK threshold when the latter recharge started. This register can be used as an indication of the leakage current during standby.
This bitfield is cleared to 0 when writing this register.

8.8.3.8 OSCCFG Register (Offset = 24h) [Reset = 00000000h]

OSCCFG is shown in #AON_PMCTRL_AON_PMCTRL_AON_PMCTRL_REGMAP_AON_PMCTRL_ALL_OSCCFG_FIGURE and described in #AON_PMCTRL_AON_PMCTRL_AON_PMCTRL_REGMAP_AON_PMCTRL_ALL_OSCCFG_TABLE.

Return to the Summary Table.

Oscillator Configuration
This register sets the period for Amplitude compensation requests sent to the oscillator control system. The amplitude compensations is only applicable when XOSC_HF is running in low power mode.

Figure 8-101 OSCCFG Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDPER_MPER_E
R-0hR/W-0hR/W-0h
Table 8-108 OSCCFG Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-3PER_MR/W0hInternal. Only to be used through TI provided API.
2-0PER_ER/W0hInternal. Only to be used through TI provided API.

8.8.3.9 RESETCTL Register (Offset = 28h) [Reset = 000001C0h]

RESETCTL is shown in #AON_PMCTRL_AON_PMCTRL_AON_PMCTRL_REGMAP_AON_PMCTRL_ALL_RESETCTL_FIGURE and described in #AON_PMCTRL_AON_PMCTRL_AON_PMCTRL_REGMAP_AON_PMCTRL_ALL_RESETCTL_TABLE.

Return to the Summary Table.

Reset Management
This register contains bitfields related to system reset such as reset source and reset request and control of brown out resets.

Figure 8-102 RESETCTL Register
3130292827262524
SYSRESETRESERVEDBOOT_DET_1_CLRBOOT_DET_0_CLR
W-0hR-0hW-0hW-0h
2322212019181716
RESERVEDBOOT_DET_1_SETBOOT_DET_0_SET
R-0hW-0hW-0h
15141312111098
WU_FROM_SDGPIO_WU_FROM_SDBOOT_DET_1BOOT_DET_0RESERVEDVDDS_LOSS_EN
R-0hR-0hR-0hR-0hR-0hR/W-1h
76543210
VDDR_LOSS_ENVDD_LOSS_ENCLK_LOSS_ENMCU_WARM_RESETRESET_SRCRESERVED
R/W-1hR/W-1hR/W-0hR/W1C-0hR-0hR-0h
Table 8-109 RESETCTL Register Field Descriptions
BitFieldTypeResetDescription
31SYSRESETW0hCold reset register. Writing 1 to this bitfield will reset the entire chip and cause boot code to run again.
0: No effect
1: Generate system reset. Appears as SYSRESET in RESET_SRC
30-26RESERVEDR0hReserved
25BOOT_DET_1_CLRW0hInternal. Only to be used through TI provided API.
24BOOT_DET_0_CLRW0hInternal. Only to be used through TI provided API.
23-18RESERVEDR0hReserved
17BOOT_DET_1_SETW0hInternal. Only to be used through TI provided API.
16BOOT_DET_0_SETW0hInternal. Only to be used through TI provided API.
15WU_FROM_SDR0hA Wakeup from SHUTDOWN on an IO event has occurred, or a wakeup from SHUTDOWN has occurred as a result of the debugger being attached.. (TCK pin being forced low)
Please refer to IOC:IOCFGn.WU_CFG for configuring the IO's as wakeup sources.
0: Wakeup occurred from cold reset or brown out as seen in RESET_SRC
1: A wakeup has occurred from SHUTDOWN
Note: This flag will be cleared when SLEEPCTL.IO_PAD_SLEEP_DIS is asserted.
14GPIO_WU_FROM_SDR0hA wakeup from SHUTDOWN on an IO event has occurred
Please refer to IOC:IOCFGn.WU_CFG for configuring the IO's as wakeup sources.
0: The wakeup did not occur from SHUTDOWN on an IO event
1: A wakeup from SHUTDOWN occurred from an IO event
The case where WU_FROM_SD is asserted but this bitfield is not asserted will only occur in a debug session. The boot code will not proceed with wakeup from SHUTDOWN procedure until this bitfield is asserted as well.
Note: This flag will be cleared when SLEEPCTL.IO_PAD_SLEEP_DIS is asserted.
13BOOT_DET_1R0hInternal. Only to be used through TI provided API.
12BOOT_DET_0R0hInternal. Only to be used through TI provided API.
11-9RESERVEDR0hReserved
8VDDS_LOSS_ENR/W1hControls reset generation in case VDDS is lost
0: Brown out detect of VDDS is ignored, unless VDDS_LOSS_EN_OVR=1
1: Brown out detect of VDDS generates system reset
7VDDR_LOSS_ENR/W1hControls reset generation in case VDDR is lost
0: Brown out detect of VDDR is ignored, unless VDDR_LOSS_EN_OVR=1
1: Brown out detect of VDDR generates system reset
6VDD_LOSS_ENR/W1hControls reset generation in case VDD is lost
0: Brown out detect of VDD is ignored, unless VDD_LOSS_EN_OVR=1
1: Brown out detect of VDD generates system reset
5CLK_LOSS_ENR/W0hControls reset generation in case SCLK_LF, SCLK_MF or SCLK_HF is lost when clock loss detection is enabled by [ANATOP_MMAP:DDI_0_OSC:CTL0.CLK_LOSS_EN]
0: Clock loss is ignored
1: Clock loss generates system reset
Note: Clock loss reset generation must be disabled when changing clock source for SCLK_LF. Failure to do so may result in a spurious system reset. Clock loss reset generation is controlled by [ANATOP_MMAP:DDI_0_OSC:CTL0.CLK_LOSS_EN]
4MCU_WARM_RESETR/W1C0hInternal. Only to be used through TI provided API.
3-1RESET_SRCR0hShows the root cause of the last system reset. More than the reported reset source can have been active during the last system reset but only the root cause is reported.
The capture feature is not rearmed until all off the possible reset sources have been released and the result has been copied to AON_PMCTL. During the copy and rearm process it is one 2MHz period in which and eventual new system reset will be reported as Power on reset regardless of the root cause.

0h = Power on reset

1h = Reset pin

2h = Brown out detect on VDDS

4h = Brown out detect on VDDR

5h = SCLK_LF, SCLK_MF or SCLK_HF clock loss detect

6h = Software reset via SYSRESET or hardware power management timeout detection.
Note: The hardware power management timeout circuit is always enabled.

7h = Software reset via PRCM warm reset request

0RESERVEDR0hReserved

8.8.3.10 SLEEPCTL Register (Offset = 2Ch) [Reset = 00000000h]

SLEEPCTL is shown in #AON_PMCTRL_AON_PMCTRL_AON_PMCTRL_REGMAP_AON_PMCTRL_ALL_SLEEPCTL_FIGURE and described in #AON_PMCTRL_AON_PMCTRL_AON_PMCTRL_REGMAP_AON_PMCTRL_ALL_SLEEPCTL_TABLE.

Return to the Summary Table.

Sleep Control
This register is used to unfreeze the IO pad ring after waking up from SHUTDOWN

Figure 8-103 SLEEPCTL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDIO_PAD_SLEEP_DIS
R-0hR/W-0h
Table 8-110 SLEEPCTL Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0IO_PAD_SLEEP_DISR/W0hControls the I/O pad sleep mode. The boot code will set this bitfield automatically unless waking up from a SHUTDOWN ( RESETCTL.WU_FROM_SD is set).
0: I/O pad sleep mode is enabled, meaning all outputs and pad configurations are latched. Inputs are transparent if pad is configured as input before IO_PAD_SLEEP_DIS is set to 1
1: I/O pad sleep mode is disabled
Application software must reconfigure the state for all IO's before setting this bitfield upon waking up from a SHUTDOWN to avoid glitches on pins.

8.8.3.11 JTAGCFG Register (Offset = 34h) [Reset = 00000100h]

JTAGCFG is shown in #AON_PMCTRL_AON_PMCTRL_AON_PMCTRL_REGMAP_AON_PMCTRL_ALL_JTAGCFG_FIGURE and described in #AON_PMCTRL_AON_PMCTRL_AON_PMCTRL_REGMAP_AON_PMCTRL_ALL_JTAGCFG_TABLE.

Return to the Summary Table.

JTAG Configuration
This register contains control for configuration of the JTAG domain. This includes permissions for each TAP.

Figure 8-104 JTAGCFG Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDJTAG_PD_FORCE_ON
R-0hR/W-1h
76543210
RESERVED
R-0h
Table 8-111 JTAGCFG Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0hReserved
8JTAG_PD_FORCE_ONR/W1hControls JTAG Power domain power state:
0: Controlled exclusively by debug subsystem. (JTAG Power domain will be powered off unless a debugger is attached)
1: JTAG Power Domain is forced on, independent of debug subsystem.
Note: The reset value causes JTAG Power domain to be powered on by default. Software must clear this bit to turn off the JTAG Power domain
7-0RESERVEDR0hReserved

8.8.3.12 JTAGUSERCODE Register (Offset = 3Ch) [Reset = 0B99A02Fh]

JTAGUSERCODE is shown in #AON_PMCTRL_AON_PMCTRL_AON_PMCTRL_REGMAP_AON_PMCTRL_ALL_JTAGUSERCODE_FIGURE and described in #AON_PMCTRL_AON_PMCTRL_AON_PMCTRL_REGMAP_AON_PMCTRL_ALL_JTAGUSERCODE_TABLE.

Return to the Summary Table.

JTAG USERCODE
Boot code copies the JTAG USERCODE to this register from where it is forwarded to the debug subsystem.

Figure 8-105 JTAGUSERCODE Register
313029282726252423222120191817161514131211109876543210
USER_CODE
R/W-0B99A02Fh
Table 8-112 JTAGUSERCODE Register Field Descriptions
BitFieldTypeResetDescription
31-0USER_CODER/W0B99A02Fh32-bit JTAG USERCODE register feeding main JTAG TAP
Note: This field can be locked by LOCKCFG.LOCK