SWCU192 User guide

SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7

1
1. 2
2. 3
3. 4
4. 5
5. 6
7
1. 8
2. 9
3. 10
  1. 11
    1. 12
    2. 13
    3. 14
    4. 15
  2. 16
    1. 17
    2. 18
    3. 19
  3. 20
  4. 21
  5. 22
    1. 23
    2. 24
  6. 25
  7. 26
  8. 27
    1. 28
    2. 29
    3. 30
    4. 31
  9. 32
  10. 33
  11. 34
  12. 35
  13. 36
    1. 37
      1. 38
      2. 39
      3. 40
      4. 41
    2. 42
43
1. 44
2. 45
3. 46
  1. 47
  2. 48
  3. 49
  4. 50
  5. 51
  6. 52
4. 53
  1. 54
  2. 55
  3. 56
  4. 57
5. 58
  1. 59
  2. 60
    1. 61
    2. 62
    3. 63
    4. 64
    5. 65
    6. 66
    7. 67
    8. 68
    9. 69
    10. 70
    11. 71
    12. 72
    13. 73
    14. 74
    15. 75
    16. 76
    17. 77
    18. 78
    19. 79
    20. 80
    21. 81
6. 82
  1. 83
  2. 84
  3. 85
7. 86
  1. 87
  2. 88
    1. 89
    2. 90
      1. 91
      2. 92
      3. 93
    3. 94
    4. 95
    5. 96
    6. 97
      1. 98
      2. 99
      3. 100
    7. 101
  3. 102
    1. 103
      1. 104
8. 105
  1. 106
  2. 107
  3. 108
9. 109
  1. 110
  2. 111
  3. 112
  4. 113
  5. 114
115
1. 116
117
1. 118
2. 119
  1. 120
  2. 121
    1. 122
    2. 123
  3. 124
  4. 125
  5. 126
  6. 127
  7. 128
129
1. 130
  1. 131
  2. 132
  3. 133
  4. 134
  5. 135
  6. 136
  7. 137
    1. 138
    2. 139
2. 140
  1. 141
  2. 142
  3. 143
  4. 144
3. 145
  1. 146
  2. 147
    1. 148
4. 149
  1. 150
  2. 151
    1. 152
    2. 153
    3. 154
5. 155
  1. 156
  2. 157
    1. 158
    2. 159
    3. 160
6. 161
7. 162
  1. 163
  2. 164
165
1. 166
2. 167
  1. 168
    1. 169
  2. 170
    1. 171
    2. 172
    3. 173
3. 174
  1. 175
    1. 176
    2. 177
  2. 178
    1. 179
    2. 180
    3. 181
    4. 182
    5. 183
    6. 184
    7. 185
    8. 186
  3. 187
  4. 188
    1. 189
      1. 190
      2. 191
      3. 192
    2. 193
      1. 194
    3. 195
      1. 196
4. 197
5. 198
6. 199
7. 200
8. 201
9. 202
10. 203
204
1. 205
2. 206
3. 207
  1. 208
4. 209
  1. 210
    1. 211
  2. 212
    1. 213
5. 214
  1. 215
    1. 216
  2. 217
    1. 218
    2. 219
    3. 220
  3. 221
6. 222
  1. 223
  2. 224
  3. 225
  4. 226
  5. 227
7. 228
  1. 229
    1. 230
    2. 231
    3. 232
  2. 233
  3. 234
8. 235
  1. 236
  2. 237
  3. 238
239
1. 240
2. 241
  1. 242
    1. 243
    2. 244
    3. 245
  2. 246
  3. 247
  4. 248
3. 249
  1. 250
  2. 251
    1. 252
    2. 253
    3. 254
4. 255
5. 256
  1. 257
  2. 258
  3. 259
  4. 260
6. 261
7. 262
  1. 263
  2. 264
265
1. 266
2. 267
3. 268
4. 269
5. 270
6. 271
7. 272
  1. 273
  2. 274
275
1. 276
  1. 277
  2. 278
2. 279
  1. 280
    1. 281
  2. 282
    1. 283
      1. 284
    2. 285
  3. 286
    1. 287
    2. 288
    3. 289
    4. 290
    5. 291
    6. 292
    7. 293
    8. 294
    9. 295
    10. 296
    11. 297
    12. 298
    13. 299
300
1. 301
2. 302
  1. 303
3. 304
4. 305
  1. 306
307
1. 308
2. 309
  1. 310
  2. 311
3. 312
4. 313
  1. 314
  2. 315
  3. 316
5. 317
  1. 318
  2. 319
  3. 320
    1. 321
    2. 322
  4. 323
    1. 324
      1. 325
    2. 326
      1. 327
    3. 328
  5. 329
    1. 330
    2. 331
    3. 332
    4. 333
    5. 334
  6. 335
    1. 336
    2. 337
    3. 338
    4. 339
    5. 340
6. 341
  1. 342
  2. 343
7. 344
  1. 345
  2. 346
    1. 347
    2. 348
    3. 349
  3. 350
    1. 351
    2. 352
      1. 353
      2. 354
      3. 355
    3. 356
      1. 357
    4. 358
      1. 359
      2. 360
  4. 361
    1. 362
    2. 363
      1. 364
    3. 365
      1. 366
      2. 367
      3. 368
      4. 369
    4. 370
      1. 371
    5. 372
      1. 373
    6. 374
      1. 375
  5. 376
    1. 377
    2. 378
    3. 379
      1. 380
      2. 381
        
        382
      3.        383
        
                384
        
                385
        
                 386
        
                 387
        
                 388
        
                 389
        
                 390
        
                 391
        
                 392
        
                 393
        
                394
        
                395
        
                396
8. 397
  1. 398
    1. 399
    2. 400
  2. 401
9. 402
  1. 403
404
1. 405
2. 406
3. 407
  1. 408
  2. 409
  3. 410
  4. 411
4. 412
  1. 413
5. 414
6. 415
7. 416
8. 417
9. 418
  1. 419
    1. 420
    2. 421
10. 422
  1. 423
  2. 424
  3. 425
426
1. 427
2. 428
3. 429
  1. 430
  2. 431
  3. 432
  4. 433
    1. 434
    2. 435
  5. 436
  6. 437
    1. 438
    2. 439
    3. 440
    4. 441
    5. 442
    6. 443
  7. 444
  8. 445
  9. 446
  10. 447
4. 448
  1. 449
  2. 450
    1. 451
    2. 452
    3. 453
5. 454
  1. 455
456
1. 457
2. 458
3. 459
  1. 460
  2. 461
    1. 462
    2. 463
    3. 464
    4. 465
    5. 466
  3. 467
  4. 468
4. 469
  1. 470
  2. 471
  3. 472
  4. 473
  5. 474
5. 475
  1. 476
477
1. 478
2. 479
  1. 480
  2. 481
  3. 482
    1. 483
  4. 484
3. 485
  1. 486
  2. 487
  3. 488
4. 489
  1. 490
491
1. 492
2. 493
3. 494
4. 495
  1. 496
497
1. 498
2. 499
3. 500
4. 501
5. 502
  1. 503
  2. 504
  3. 505
6. 506
  1. 507
    1. 508
    2. 509
    3. 510
      1. 511
      2. 512
7. 513
  1. 514
515
1. 516
  1. 517
2. 518
  1. 519
    1. 520
  2. 521
    1. 522
    2. 523
  3. 524
  4. 525
3. 526
  1. 527
    1. 528
    2. 529
    3. 530
    4. 531
  2. 532
    1. 533
      1. 534
    2. 535
      1. 536
      2. 537
    3. 538
      1. 539
    4. 540
      1. 541
      2. 542
      3. 543
    5. 544
    6. 545
    7. 546
    8. 547
    9. 548
    10. 549
4. 550
  1. 551
    1. 552
  2. 553
    1. 554
    2. 555
      1. 556
      2. 557
      3. 558
      4. 559
      5. 560
  3. 561
    1. 562
    2. 563
    3. 564
  4. 565
    1. 566
    2. 567
      1. 568
      2. 569
      3. 570
  5. 571
    1. 572
    2. 573
      1. 574
      2. 575
      3. 576
      4.        577
        
                578
        
                579
      5. 580
      6. 581
    3. 582
      1. 583
      2. 584
      3.        585
        
                586
        
                587
        
                588
        
                589
      4. 590
  6. 591
    1. 592
    2. 593
  7. 594
    1. 595
    2. 596
      1. 597
      2. 598
      3. 599
      4. 600
      5.        601
        
                602
        
                 603
        
                604
        
                 605
        
                606
        
                 607
      6. 608
5. 609
  1. 610
    1. 611
    2. 612
  2. 613
    1. 614
    2. 615
      1. 616
      2. 617
      3. 618
      4. 619
      5. 620
      6. 621
      7. 622
      8. 623
  3. 624
    1. 625
    2. 626
      1. 627
      2. 628
      3. 629
      4. 630
  4. 631
    1. 632
    2. 633
      1. 634
      2. 635
      3.        636
        
                637
        
                638
  5. 639
    1. 640
    2. 641
      1. 642
      2. 643
      3.        644
        
                645
        
                646
        
                647
      4.        648
        
                649
        
                650
        
                651
        
                652
      5. 653
      6. 654
  6. 655
    1. 656
    2. 657
      1. 658
      2. 659
      3. 660
      4. 661
      5. 662
6. 663
  1. 664
    1. 665
    2. 666
      1.        667
        
                668
        
                669
  2. 670
  3. 671
  4. 672
  5. 673
  6. 674
  7. 675
7. 676
8. 677
  1. 678
  2. 679
  3. 680
  4. 681
  5. 682
  6. 683
  7. 684
  8. 685
  9. 686
  10. 687
  11. 688
  12. 689
690
1. 691
2. 692
3. 693
  1. 694
695
1. 696
2. 697
3. 698
4. 699
  1. 700
  2. 701
  3. 702
  4. 703
    1. 704
    2. 705
      1. 706
      2. 707
  5. 708
  6. 709
  7. 710
5. 711
6. 712
7. 713
  1. 714
715
1. 716
2. 717
3. 718
4. 719
  1. 720
  2. 721
    1. 722
    2. 723
  3. 724
  4. 725
    1. 726
    2. 727
      1. 728
      2. 729
    3. 730
    4. 731
    5. 732
    6. 733
    7. 734
5. 735
6. 736
7. 737
  1. 738
739
1. 740
2. 741
3. 742
  1. 743
    1. 744
    2. 745
    3. 746
    4. 747
    5. 748
  2. 749
    1. 750
  3. 751
    1. 752
    2. 753
  4. 754
  5. 755
    1. 756
    2. 757
4. 758
5. 759
  1. 760
761
1. 762
2. 763
3. 764
4. 765
  1. 766
    1. 767
  2. 768
  3. 769
  4. 770
    1. 771
  5. 772
    1. 773
  6. 774
    1. 775
  7. 776
    1. 777
  8. 778
    1. 779
    2. 780
5. 781
  1. 782
  2. 783
  3. 784
  4. 785
    1. 786
    2. 787
    3. 788
6. 789
  1. 790
  2. 791
  3. 792
  4. 793
7. 794
8. 795
  1. 796
  2. 797
9. 798
  1. 799
800
1. 801
  1. 802
2. 803
  1. 804
  2. 805
  3. 806
    1. 807
    2. 808
    3. 809
  4. 810
    1. 811
    2. 812
    3. 813
3. 814
  1. 815
  2. 816
    1. 817
    2. 818
    3. 819
    4. 820
    5. 821
      1. 822
      2. 823
      3. 824
    6. 825
      1. 826
    7. 827
      1. 828
      2. 829
      3. 830
      4. 831
    8. 832
  3. 833
    1. 834
      1. 835
      2. 836
      3. 837
      4. 838
      5. 839
      6. 840
      7. 841
      8. 842
      9. 843
      10. 844
      11. 845
      12. 846
      13. 847
      14. 848
    2. 849
      1. 850
      2. 851
      3. 852
      4. 853
      5. 854
      6. 855
      7. 856
      8. 857
      9. 858
      10. 859
      11. 860
      12. 861
      13. 862
      14. 863
      15. 864
      16. 865
      17. 866
      18. 867
      19. 868
      20. 869
  4. 870
    1. 871
    2. 872
    3. 873
    4. 874
    5. 875
4. 876
  1. 877
    1. 878
    2. 879
    3. 880
    4. 881
    5. 882
  2. 883
    1. 884
    2. 885
5. 886
  1. 887
    1. 888
    2. 889
    3. 890
    4. 891
  2. 892
  3. 893
    1. 894
    2. 895
  4. 896
    1. 897
      1.        898
        
                899
        
                900
      2. 901
      3. 902
      4. 903
      5. 904
    2. 905
    3. 906
    4. 907
    5. 908
    6. 909
  5. 910
    1. 911
    2. 912
    3. 913
    4. 914
    5. 915
    6. 916
6. 917
  1. 918
    1. 919
      1. 920
    2. 921
    3. 922
    4. 923
  2. 924
7. 925
  1. 926
  2. 927
8. 928
  1. 929
  2. 930
  3. 931
  4. 932
  5. 933
  6. 934
  7. 935
  8. 936
    1. 937
    2. 938
    3. 939
    4. 940
  9. 941
    1. 942
    2. 943
    3. 944
  10. 945
    1. 946
    2. 947
    3. 948
    4. 949
    5. 950
  11. 951
    1. 952
    2. 953
    3. 954
    4. 955
    5. 956
  12. 957
  13. 958
  14. 959
  15. 960
  16. 961
  17. 962
9. 963
  1. 964
10. 965
  1. 966
  2. 967
    1. 968
      1. 969
    2. 970
    3. 971
  3. 972
  4. 973
    1. 974
    2. 975
  5. 976
    1. 977
    2. 978
      1. 979
    3. 980
      1. 981
      2. 982
    4. 983
      1. 984
      2. 985
    5. 986
      1. 987
      2. 988
      3. 989
  6. 990
    1. 991
    2. 992
11. 993
  1. 994
  2. 995
  3. 996
997

9.7.1 FLASH_MMR Registers

#FLASH_MMR_FLASH_MMR_MMAP2_TABLE_1 lists the memory-mapped registers for the FLASH_MMR registers. All register offset addresses not listed in #FLASH_MMR_FLASH_MMR_MMAP2_TABLE_1 should be considered as reserved locations and the register contents should not be modified.

Table 9-3 FLASH_MMR Registers

Offset	Acronym	Register Name	Section
1Ch	STAT	FMC and Efuse Status	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_STAT
24h	CFG	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_CFG
2Ch	FLASH_SIZE	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FLASH_SIZE
3Ch	FWLOCK	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FWLOCK
40h	FWFLAG	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FWFLAG
1000h	EFUSE	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_EFUSE
1004h	EFUSEADDR	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_EFUSEADDR
1008h	DATAUPPER	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_DATAUPPER
100Ch	DATALOWER	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_DATALOWER
1010h	EFUSECFG	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_EFUSECFG
1014h	EFUSESTAT	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_EFUSESTAT
1018h	ACC	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_ACC
101Ch	BOUNDARY	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_BOUNDARY
1020h	EFUSEFLAG	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_EFUSEFLAG
1024h	EFUSEKEY	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_EFUSEKEY
1028h	EFUSERELEASE	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_EFUSERELEASE
102Ch	EFUSEPINS	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_EFUSEPINS
1030h	EFUSECRA	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_EFUSECRA
1034h	EFUSEREAD	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_EFUSEREAD
1038h	EFUSEPROGRAM	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_EFUSEPROGRAM
103Ch	EFUSEERROR	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_EFUSEERROR
1040h	SINGLEBIT	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_SINGLEBIT
1044h	TWOBIT	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_TWOBIT
1048h	SELFTESTCYC	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_SELFTESTCYC
104Ch	SELFTESTSIGN	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_SELFTESTSIGN
2000h	FRDCTL	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FRDCTL
2004h	FSPRD	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSPRD
2008h	FEDACCTL1	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FEDACCTL1
201Ch	FEDACSTAT	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FEDACSTAT
2030h	FBPROT	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FBPROT
2034h	FBSE	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FBSE
2038h	FBBUSY	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FBBUSY
203Ch	FBAC	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FBAC
2040h	FBFALLBACK	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FBFALLBACK
2044h	FBPRDY	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FBPRDY
2048h	FPAC1	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FPAC1
204Ch	FPAC2	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FPAC2
2050h	FMAC	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FMAC
2054h	FMSTAT	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FMSTAT
2064h	FLOCK	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FLOCK
2080h	FVREADCT	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FVREADCT
2084h	FVHVCT1	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FVHVCT1
2088h	FVHVCT2	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FVHVCT2
208Ch	FVHVCT3	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FVHVCT3
2090h	FVNVCT	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FVNVCT
2094h	FVSLP	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FVSLP
2098h	FVWLCT	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FVWLCT
209Ch	FEFUSECTL	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FEFUSECTL
20A0h	FEFUSESTAT	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FEFUSESTAT
20A4h	FEFUSEDATA	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FEFUSEDATA
20A8h	FSEQPMP	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSEQPMP
2100h	FBSTROBES	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FBSTROBES
2104h	FPSTROBES	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FPSTROBES
2108h	FBMODE	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FBMODE
210Ch	FTCR	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FTCR
2110h	FADDR	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FADDR
211Ch	FTCTL	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FTCTL
2120h	FWPWRITE0	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FWPWRITE0
2124h	FWPWRITE1	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FWPWRITE1
2128h	FWPWRITE2	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FWPWRITE2
212Ch	FWPWRITE3	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FWPWRITE3
2130h	FWPWRITE4	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FWPWRITE4
2134h	FWPWRITE5	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FWPWRITE5
2138h	FWPWRITE6	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FWPWRITE6
213Ch	FWPWRITE7	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FWPWRITE7
2140h	FWPWRITE_ECC	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FWPWRITE_ECC
2144h	FSWSTAT	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSWSTAT
2200h	FSM_GLBCTL	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_GLBCTL
2204h	FSM_STATE	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_STATE
2208h	FSM_STAT	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_STAT
220Ch	FSM_CMD	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_CMD
2210h	FSM_PE_OSU	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_PE_OSU
2214h	FSM_VSTAT	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_VSTAT
2218h	FSM_PE_VSU	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_PE_VSU
221Ch	FSM_CMP_VSU	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_CMP_VSU
2220h	FSM_EX_VAL	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_EX_VAL
2224h	FSM_RD_H	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_RD_H
2228h	FSM_P_OH	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_P_OH
222Ch	FSM_ERA_OH	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_ERA_OH
2230h	FSM_SAV_PPUL	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_SAV_PPUL
2234h	FSM_PE_VH	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_PE_VH
2240h	FSM_PRG_PW	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_PRG_PW
2244h	FSM_ERA_PW	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_ERA_PW
2254h	FSM_SAV_ERA_PUL	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_SAV_ERA_PUL
2258h	FSM_TIMER	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_TIMER
225Ch	FSM_MODE	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_MODE
2260h	FSM_PGM	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_PGM
2264h	FSM_ERA	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_ERA
2268h	FSM_PRG_PUL	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_PRG_PUL
226Ch	FSM_ERA_PUL	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_ERA_PUL
2270h	FSM_STEP_SIZE	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_STEP_SIZE
2274h	FSM_PUL_CNTR	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_PUL_CNTR
2278h	FSM_EC_STEP_HEIGHT	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_EC_STEP_HEIGHT
227Ch	FSM_ST_MACHINE	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_ST_MACHINE
2280h	FSM_FLES	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_FLES
2288h	FSM_WR_ENA	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_WR_ENA
228Ch	FSM_ACC_PP	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_ACC_PP
2290h	FSM_ACC_EP	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_ACC_EP
22A0h	FSM_ADDR	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_ADDR
22A4h	FSM_SECTOR	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_SECTOR
22A8h	FMC_REV_ID	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FMC_REV_ID
22ACh	FSM_ERR_ADDR	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_ERR_ADDR
22B0h	FSM_PGM_MAXPUL	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_PGM_MAXPUL
22B4h	FSM_EXECUTE	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_EXECUTE
22C0h	FSM_SECTOR1	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_SECTOR1
22C4h	FSM_SECTOR2	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_SECTOR2
22E0h	FSM_BSLE0	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_BSLE0
22E4h	FSM_BSLE1	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_BSLE1
22F0h	FSM_BSLP0	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_BSLP0
22F4h	FSM_BSLP1	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_BSLP1
22F8h	FSM_PGM128	FMC FSM Enable 128-bit Wide Programming	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_PGM128
22FCh	FSM_EN_PRL_BNK_RD	FMC FSM Enable Parallell Reads for Multibanks	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_EN_PRL_BNK_RD
2400h	FCFG_BANK	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_BANK
2404h	FCFG_WRAPPER	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_WRAPPER
2408h	FCFG_BNK_TYPE	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_BNK_TYPE
2410h	FCFG_B0_START	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B0_START
2414h	FCFG_B1_START	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B1_START
2418h	FCFG_B2_START	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B2_START
241Ch	FCFG_B3_START	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B3_START
2420h	FCFG_B4_START	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B4_START
2424h	FCFG_B5_START	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B5_START
2428h	FCFG_B6_START	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B6_START
242Ch	FCFG_B7_START	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B7_START
2430h	FCFG_B0_SSIZE0	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B0_SSIZE0
2434h	FCFG_B0_SSIZE1	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B0_SSIZE1
2438h	FCFG_B0_SSIZE2	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B0_SSIZE2
243Ch	FCFG_B0_SSIZE3	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B0_SSIZE3
2440h	FCFG_B1_SSIZE0	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B1_SSIZE0
2444h	FCFG_B1_SSIZE1	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B1_SSIZE1
2448h	FCFG_B1_SSIZE2	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B1_SSIZE2
244Ch	FCFG_B1_SSIZE3	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B1_SSIZE3
2450h	FCFG_B2_SSIZE0	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B2_SSIZE0
2454h	FCFG_B2_SSIZE1	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B2_SSIZE1
2458h	FCFG_B2_SSIZE2	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B2_SSIZE2
245Ch	FCFG_B2_SSIZE3	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B2_SSIZE3
2460h	FCFG_B3_SSIZE0	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B3_SSIZE0
2464h	FCFG_B3_SSIZE1	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B3_SSIZE1
2468h	FCFG_B3_SSIZE2	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B3_SSIZE2
246Ch	FCFG_B3_SSIZE3	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B3_SSIZE3
2470h	FCFG_B4_SSIZE0	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B4_SSIZE0
2474h	FCFG_B4_SSIZE1	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B4_SSIZE1
2478h	FCFG_B4_SSIZE2	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B4_SSIZE2
247Ch	FCFG_B4_SSIZE3	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B4_SSIZE3
2480h	FCFG_B5_SSIZE0	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B5_SSIZE0
2484h	FCFG_B5_SSIZE1	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B5_SSIZE1
2488h	FCFG_B5_SSIZE2	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B5_SSIZE2
248Ch	FCFG_B5_SSIZE3	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B5_SSIZE3
2490h	FCFG_B6_SSIZE0	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B6_SSIZE0
2494h	FCFG_B6_SSIZE1	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B6_SSIZE1
2498h	FCFG_B6_SSIZE2	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B6_SSIZE2
249Ch	FCFG_B6_SSIZE3	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B6_SSIZE3
24A0h	FCFG_B7_SSIZE0	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B7_SSIZE0
24A4h	FCFG_B7_SSIZE1	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B7_SSIZE1
24A8h	FCFG_B7_SSIZE2	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B7_SSIZE2
24ACh	FCFG_B7_SSIZE3	Internal	#FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B7_SSIZE3

Complex bit access types are encoded to fit into small table cells. #FLASH_MMR_FLASH_MMR_MMAP2_LEGEND shows the codes that are used for access types in this section.

Table 9-4 FLASH_MMR Access Type Codes

Access Type	Code	Description
Read Type
R	R	Read
Write Type
W	W	Write
W1C	W 1C	Write 1 to clear
Reset or Default Value
-n		Value after reset or the default value

9.7.1.1 STAT Register (Offset = 1Ch) [Reset = 00000000h]

STAT is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_STAT_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_STAT_TABLE.

Return to the Summary Table.

FMC and Efuse Status

Figure 9-9 STAT Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
EFUSE_BLANK	EFUSE_TIMEOUT	SPRS_BYTE_NOT_OK	EFUSE_ERRCODE
R-0h	R-0h	R-0h	R-0h

7	6	5	4	3	2	1	0
RESERVED		BUSY		RESERVED		POWER_MODE
R-0h		R-0h		R-0h		R-0h

Table 9-5 STAT Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h	Reserved
15	EFUSE_BLANK	R	0h	Efuse scanning detected if fuse ROM is blank: 0 : Not blank 1 : Blank
14	EFUSE_TIMEOUT	R	0h	Efuse scanning resulted in timeout error. 0 : No Timeout error 1 : Timeout Error
13	SPRS_BYTE_NOT_OK	R	0h	Efuse scanning resulted in scan chain Sparse byte error. 0 : No Sparse error 1 : Sparse Error
12-8	EFUSE_ERRCODE	R	0h	Same as EFUSEERROR.CODE
7-6	RESERVED	R	0h	Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation
5-4	BUSY	R	0h	Fast version of the FMC FMSTAT.BUSY bit. This flag is valid immediately after the operation setting it (FMSTAT.BUSY is delayed some cycles) 0 : Not busy 1 : Busy Bit 4 is for the busy state for Bank0 which is at logical address 0x0 Bit 5 for Bank1.
3-2	RESERVED	R	0h	Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation
1-0	POWER_MODE	R	0h	Power state of each of the 2 flash bank instances in the flash sub-system. 0 : Active 1 : Low power Bit 0 is for the power state for Bank0 which is at logical address 0x0 Bit 1 for Bank1

9.7.1.2 CFG Register (Offset = 24h) [Reset = 00000000h]

CFG is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_CFG_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_CFG_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-10 CFG Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED						FORCE_STANDBY	STANDBY_MODE_SEL
R-0h						R/W-0h	R/W-0h

7	6	5	4	3	2	1	0
STANDBY_PW_SEL		DIS_EFUSECLK	DIS_READACCESS	ENABLE_SWINTF	RESERVED	DIS_STANDBY	RESERVED
R/W-0h		R/W-0h	R/W-0h	R/W-0h	R-0h	R/W-0h	R-0h

Table 9-6 CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-10	RESERVED	R	0h	Reserved
9	FORCE_STANDBY	R/W	0h	Internal. Only to be used through TI provided API.
8	STANDBY_MODE_SEL	R/W	0h	Internal. Only to be used through TI provided API.
7-6	STANDBY_PW_SEL	R/W	0h	Internal. Only to be used through TI provided API.
5	DIS_EFUSECLK	R/W	0h	Internal. Only to be used through TI provided API.
4	DIS_READACCESS	R/W	0h	Internal. Only to be used through TI provided API.
3	ENABLE_SWINTF	R/W	0h	Internal. Only to be used through TI provided API.
2	RESERVED	R	0h	Reserved
1	DIS_STANDBY	R/W	0h	Internal. Only to be used through TI provided API.
0	RESERVED	R	0h	Reserved

9.7.1.3 FLASH_SIZE Register (Offset = 2Ch) [Reset = 00000058h]

FLASH_SIZE is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FLASH_SIZE_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FLASH_SIZE_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-11 FLASH_SIZE Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																								SECTORS
R-0h																								R/W-58h

Table 9-7 FLASH_SIZE Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	RESERVED	R	0h	Reserved
7-0	SECTORS	R/W	58h	Internal. Only to be used through TI provided API.

9.7.1.4 FWLOCK Register (Offset = 3Ch) [Reset = 00000000h]

FWLOCK is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FWLOCK_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FWLOCK_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-12 FWLOCK Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED													FWLOCK
R-0h													R/W-0h

Table 9-8 FWLOCK Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2-0	FWLOCK	R/W	0h	Internal. Only to be used through TI provided API.

9.7.1.5 FWFLAG Register (Offset = 40h) [Reset = 00000000h]

FWFLAG is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FWFLAG_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FWFLAG_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-13 FWFLAG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED													FWFLAG
R-0h													R/W-0h

Table 9-9 FWFLAG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2-0	FWFLAG	R/W	0h	Internal. Only to be used through TI provided API.

9.7.1.6 EFUSE Register (Offset = 1000h) [Reset = 00000000h]

EFUSE is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_EFUSE_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_EFUSE_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-14 EFUSE Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED			INSTRUCTION					RESERVED
R-0h			R/W-0h					R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DUMPWORD
R/W-0h

Table 9-10 EFUSE Register Field Descriptions

Bit	Field	Type	Reset	Description
31-29	RESERVED	R	0h	Reserved
28-24	INSTRUCTION	R/W	0h	Internal. Only to be used through TI provided API.
23-16	RESERVED	R	0h	Reserved
15-0	DUMPWORD	R/W	0h	Internal. Only to be used through TI provided API.

9.7.1.7 EFUSEADDR Register (Offset = 1004h) [Reset = 00000000h]

EFUSEADDR is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_EFUSEADDR_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_EFUSEADDR_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-15 EFUSEADDR Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																BLOCK					ROW
R-0h																R/W-0h					R/W-0h

Table 9-11 EFUSEADDR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h	Reserved
15-11	BLOCK	R/W	0h	Internal. Only to be used through TI provided API.
10-0	ROW	R/W	0h	Internal. Only to be used through TI provided API.

9.7.1.8 DATAUPPER Register (Offset = 1008h) [Reset = 00000000h]

DATAUPPER is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_DATAUPPER_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_DATAUPPER_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-16 DATAUPPER Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED								SPARE					P	R	EEN
R-0h								R/W-0h					R/W-0h	R/W-0h	R/W-0h

Table 9-12 DATAUPPER Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	RESERVED	R	0h	Reserved
7-3	SPARE	R/W	0h	Internal. Only to be used through TI provided API.
2	P	R/W	0h	Internal. Only to be used through TI provided API.
1	R	R/W	0h	Internal. Only to be used through TI provided API.
0	EEN	R/W	0h	Internal. Only to be used through TI provided API.

9.7.1.9 DATALOWER Register (Offset = 100Ch) [Reset = 00000000h]

DATALOWER is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_DATALOWER_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_DATALOWER_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-17 DATALOWER Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DATA
R/W-0h

Table 9-13 DATALOWER Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	DATA	R/W	0h	Internal. Only to be used through TI provided API.

9.7.1.10 EFUSECFG Register (Offset = 1010h) [Reset = 00000001h]

EFUSECFG is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_EFUSECFG_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_EFUSECFG_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-18 EFUSECFG Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED							IDLEGATING
R-0h							R/W-0h

7	6	5	4	3	2	1	0
RESERVED			SLAVEPOWER		RESERVED		GATING
R-0h			R/W-0h		R-0h		R/W-1h

Table 9-14 EFUSECFG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-9	RESERVED	R	0h	Reserved
8	IDLEGATING	R/W	0h	Internal. Only to be used through TI provided API.
7-5	RESERVED	R	0h	Reserved
4-3	SLAVEPOWER	R/W	0h	Internal. Only to be used through TI provided API.
2-1	RESERVED	R	0h	Reserved
0	GATING	R/W	1h	Internal. Only to be used through TI provided API.

9.7.1.11 EFUSESTAT Register (Offset = 1014h) [Reset = 00000001h]

EFUSESTAT is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_EFUSESTAT_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_EFUSESTAT_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-19 EFUSESTAT Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED							RESETDONE
R-0h							R-1h

Table 9-15 EFUSESTAT Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h	Reserved
0	RESETDONE	R	1h	Internal. Only to be used through TI provided API.

9.7.1.12 ACC Register (Offset = 1018h) [Reset = 00000000h]

ACC is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_ACC_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_ACC_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-20 ACC Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED								ACCUMULATOR
R-0h								R-0h

Table 9-16 ACC Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RESERVED	R	0h	Reserved
23-0	ACCUMULATOR	R	0h	Internal. Only to be used through TI provided API.

9.7.1.13 BOUNDARY Register (Offset = 101Ch) [Reset = 00000000h]

BOUNDARY is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_BOUNDARY_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_BOUNDARY_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-21 BOUNDARY Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
DISROW0	SPARE	EFC_SELF_TEST_ERROR	EFC_INSTRUCTION_INFO	EFC_INSTRUCTION_ERROR	EFC_AUTOLOAD_ERROR	OUTPUTENABLE
R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

15	14	13	12	11	10	9	8
OUTPUTENABLE		SYS_ECC_SELF_TEST_EN	SYS_ECC_OVERRIDE_EN	EFC_FDI	SYS_DIEID_AUTOLOAD_EN	SYS_REPAIR_EN
R/W-0h		R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

7	6	5	4	3	2	1	0
SYS_WS_READ_STATES				INPUTENABLE
R/W-0h				R/W-0h

Table 9-17 BOUNDARY Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RESERVED	R	0h	Reserved
23	DISROW0	R/W	0h	Internal. Only to be used through TI provided API.
22	SPARE	R/W	0h	Internal. Only to be used through TI provided API.
21	EFC_SELF_TEST_ERROR	R/W	0h	Internal. Only to be used through TI provided API.
20	EFC_INSTRUCTION_INFO	R/W	0h	Internal. Only to be used through TI provided API.
19	EFC_INSTRUCTION_ERROR	R/W	0h	Internal. Only to be used through TI provided API.
18	EFC_AUTOLOAD_ERROR	R/W	0h	Internal. Only to be used through TI provided API.
17-14	OUTPUTENABLE	R/W	0h	Internal. Only to be used through TI provided API.
13	SYS_ECC_SELF_TEST_EN	R/W	0h	Internal. Only to be used through TI provided API.
12	SYS_ECC_OVERRIDE_EN	R/W	0h	Internal. Only to be used through TI provided API.
11	EFC_FDI	R/W	0h	Internal. Only to be used through TI provided API.
10	SYS_DIEID_AUTOLOAD_EN	R/W	0h	Internal. Only to be used through TI provided API.
9-8	SYS_REPAIR_EN	R/W	0h	Internal. Only to be used through TI provided API.
7-4	SYS_WS_READ_STATES	R/W	0h	Internal. Only to be used through TI provided API.
3-0	INPUTENABLE	R/W	0h	Internal. Only to be used through TI provided API.

9.7.1.14 EFUSEFLAG Register (Offset = 1020h) [Reset = 00000000h]

EFUSEFLAG is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_EFUSEFLAG_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_EFUSEFLAG_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-22 EFUSEFLAG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED															KEY
R-0h															R-0h

Table 9-18 EFUSEFLAG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h	Reserved
0	KEY	R	0h	Internal. Only to be used through TI provided API.

9.7.1.15 EFUSEKEY Register (Offset = 1024h) [Reset = 00000000h]

EFUSEKEY is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_EFUSEKEY_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_EFUSEKEY_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-23 EFUSEKEY Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CODE
R/W-0h

Table 9-19 EFUSEKEY Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	CODE	R/W	0h	Internal. Only to be used through TI provided API.

9.7.1.16 EFUSERELEASE Register (Offset = 1028h) [Reset = X]

EFUSERELEASE is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_EFUSERELEASE_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_EFUSERELEASE_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-24 EFUSERELEASE Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ODPYEAR							ODPMONTH				ODPDAY
R-X							R-X				R-X

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
EFUSEYEAR							EFUSEMONTH				EFUSEDAY
R-X							R-X				R-X

Table 9-20 EFUSERELEASE Register Field Descriptions

Bit	Field	Type	Reset	Description
31-25	ODPYEAR	R	X	Internal. Only to be used through TI provided API.
24-21	ODPMONTH	R	X	Internal. Only to be used through TI provided API.
20-16	ODPDAY	R	X	Internal. Only to be used through TI provided API.
15-9	EFUSEYEAR	R	X	Internal. Only to be used through TI provided API.
8-5	EFUSEMONTH	R	X	Internal. Only to be used through TI provided API.
4-0	EFUSEDAY	R	X	Internal. Only to be used through TI provided API.

9.7.1.17 EFUSEPINS Register (Offset = 102Ch) [Reset = X]

EFUSEPINS is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_EFUSEPINS_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_EFUSEPINS_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-25 EFUSEPINS Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
EFC_SELF_TEST_DONE	EFC_SELF_TEST_ERROR	SYS_ECC_SELF_TEST_EN	EFC_INSTRUCTION_INFO	EFC_INSTRUCTION_ERROR	EFC_AUTOLOAD_ERROR	SYS_ECC_OVERRIDE_EN	EFC_READY
R-X	R-X	R-X	R-X	R-X	R-X	R-X	R-X

7	6	5	4	3	2	1	0
EFC_FCLRZ	SYS_DIEID_AUTOLOAD_EN	SYS_REPAIR_EN		SYS_WS_READ_STATES
R-X	R-X	R-X		R-X

Table 9-21 EFUSEPINS Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h	Internal. Only to be used through TI provided API.
15	EFC_SELF_TEST_DONE	R	X	Internal. Only to be used through TI provided API.
14	EFC_SELF_TEST_ERROR	R	X	Internal. Only to be used through TI provided API.
13	SYS_ECC_SELF_TEST_EN	R	X	Internal. Only to be used through TI provided API.
12	EFC_INSTRUCTION_INFO	R	X	Internal. Only to be used through TI provided API.
11	EFC_INSTRUCTION_ERROR	R	X	Internal. Only to be used through TI provided API.
10	EFC_AUTOLOAD_ERROR	R	X	Internal. Only to be used through TI provided API.
9	SYS_ECC_OVERRIDE_EN	R	X	Internal. Only to be used through TI provided API.
8	EFC_READY	R	X	Internal. Only to be used through TI provided API.
7	EFC_FCLRZ	R	X	Internal. Only to be used through TI provided API.
6	SYS_DIEID_AUTOLOAD_EN	R	X	Internal. Only to be used through TI provided API.
5-4	SYS_REPAIR_EN	R	X	Internal. Only to be used through TI provided API.
3-0	SYS_WS_READ_STATES	R	X	Internal. Only to be used through TI provided API.

9.7.1.18 EFUSECRA Register (Offset = 1030h) [Reset = 00000000h]

EFUSECRA is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_EFUSECRA_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_EFUSECRA_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-26 EFUSECRA Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																										DATA
R-0h																										R/W-0h

Table 9-22 EFUSECRA Register Field Descriptions

Bit	Field	Type	Reset	Description
31-6	RESERVED	R	0h	Reserved
5-0	DATA	R/W	0h	Internal. Only to be used through TI provided API.

9.7.1.19 EFUSEREAD Register (Offset = 1034h) [Reset = 00000000h]

EFUSEREAD is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_EFUSEREAD_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_EFUSEREAD_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-27 EFUSEREAD Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED						DATABIT
R-0h						R/W-0h

7	6	5	4	3	2	1	0
READCLOCK				DEBUG	SPARE	MARGIN
R/W-0h				R/W-0h	R/W-0h	R/W-0h

Table 9-23 EFUSEREAD Register Field Descriptions

Bit	Field	Type	Reset	Description
31-10	RESERVED	R	0h	Reserved
9-8	DATABIT	R/W	0h	Internal. Only to be used through TI provided API.
7-4	READCLOCK	R/W	0h	Internal. Only to be used through TI provided API.
3	DEBUG	R/W	0h	Internal. Only to be used through TI provided API.
2	SPARE	R/W	0h	Internal. Only to be used through TI provided API.
1-0	MARGIN	R/W	0h	Internal. Only to be used through TI provided API.

9.7.1.20 EFUSEPROGRAM Register (Offset = 1038h) [Reset = 00000000h]

EFUSEPROGRAM is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_EFUSEPROGRAM_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_EFUSEPROGRAM_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-28 EFUSEPROGRAM Register

31	30	29	28	27	26	25	24
RESERVED	COMPAREDISABLE	CLOCKSTALL
R-0h	R/W-0h	R/W-0h

23	22	21	20	19	18	17	16
CLOCKSTALL
R/W-0h

15	14	13	12	11	10	9	8
CLOCKSTALL		VPPTOVDD	ITERATIONS				WRITECLOCK
R/W-0h		R/W-0h	R/W-0h				R/W-0h

7	6	5	4	3	2	1	0
WRITECLOCK
R/W-0h

Table 9-24 EFUSEPROGRAM Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESERVED	R	0h	Reserved
30	COMPAREDISABLE	R/W	0h	Internal. Only to be used through TI provided API.
29-14	CLOCKSTALL	R/W	0h	Internal. Only to be used through TI provided API.
13	VPPTOVDD	R/W	0h	Internal. Only to be used through TI provided API.
12-9	ITERATIONS	R/W	0h	Internal. Only to be used through TI provided API.
8-0	WRITECLOCK	R/W	0h	Internal. Only to be used through TI provided API.

9.7.1.21 EFUSEERROR Register (Offset = 103Ch) [Reset = 00000000h]

EFUSEERROR is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_EFUSEERROR_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_EFUSEERROR_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-29 EFUSEERROR Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED		DONE	CODE
R-0h		R/W-0h	R/W-0h

Table 9-25 EFUSEERROR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-6	RESERVED	R	0h	Reserved
5	DONE	R/W	0h	Internal. Only to be used through TI provided API.
4-0	CODE	R/W	0h	Internal. Only to be used through TI provided API.

9.7.1.22 SINGLEBIT Register (Offset = 1040h) [Reset = 00000000h]

SINGLEBIT is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_SINGLEBIT_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_SINGLEBIT_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-30 SINGLEBIT Register

31	30	29	28	27	26	25	24
FROMN
R-0h

23	22	21	20	19	18	17	16
FROMN
R-0h

15	14	13	12	11	10	9	8
FROMN
R-0h

7	6	5	4	3	2	1	0
FROMN							FROM0
R-0h							R-0h

Table 9-26 SINGLEBIT Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	FROMN	R	0h	Internal. Only to be used through TI provided API.
0	FROM0	R	0h	Internal. Only to be used through TI provided API.

9.7.1.23 TWOBIT Register (Offset = 1044h) [Reset = 00000000h]

TWOBIT is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_TWOBIT_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_TWOBIT_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-31 TWOBIT Register

31	30	29	28	27	26	25	24
FROMN
R-0h

23	22	21	20	19	18	17	16
FROMN
R-0h

15	14	13	12	11	10	9	8
FROMN
R-0h

7	6	5	4	3	2	1	0
FROMN							FROM0
R-0h							R-0h

Table 9-27 TWOBIT Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	FROMN	R	0h	Internal. Only to be used through TI provided API.
0	FROM0	R	0h	Internal. Only to be used through TI provided API.

9.7.1.24 SELFTESTCYC Register (Offset = 1048h) [Reset = 00000000h]

SELFTESTCYC is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_SELFTESTCYC_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_SELFTESTCYC_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-32 SELFTESTCYC Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CYCLES
R/W-0h

Table 9-28 SELFTESTCYC Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	CYCLES	R/W	0h	Internal. Only to be used through TI provided API.

9.7.1.25 SELFTESTSIGN Register (Offset = 104Ch) [Reset = 00000000h]

SELFTESTSIGN is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_SELFTESTSIGN_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_SELFTESTSIGN_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-33 SELFTESTSIGN Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SIGNATURE
R/W-0h

Table 9-29 SELFTESTSIGN Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	SIGNATURE	R/W	0h	Internal. Only to be used through TI provided API.

9.7.1.26 FRDCTL Register (Offset = 2000h) [Reset = 00000200h]

FRDCTL is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FRDCTL_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FRDCTL_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-34 FRDCTL Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED				RWAIT				RESERVED
R-0h				R/W-2h				R-0h

Table 9-30 FRDCTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-12	RESERVED	R	0h	Reserved
11-8	RWAIT	R/W	2h	Internal. Only to be used through TI provided API.
7-0	RESERVED	R	0h	Reserved

9.7.1.27 FSPRD Register (Offset = 2004h) [Reset = 00000000h]

FSPRD is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSPRD_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSPRD_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-35 FSPRD Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RMBSEM								RESERVED						RM1	RM0
R/W-0h								R-0h						R/W-0h	R/W-0h

Table 9-31 FSPRD Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h	Reserved
15-8	RMBSEM	R/W	0h	Internal. Only to be used through TI provided API.
7-2	RESERVED	R	0h	Reserved
1	RM1	R/W	0h	Internal. Only to be used through TI provided API.
0	RM0	R/W	0h	Internal. Only to be used through TI provided API.

9.7.1.28 FEDACCTL1 Register (Offset = 2008h) [Reset = 00000000h]

FEDACCTL1 is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FEDACCTL1_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FEDACCTL1_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-36 FEDACCTL1 Register

31	30	29	28	27	26	25	24
RESERVED							SUSP_IGNR
R-0h							R/W-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED
R-0h

Table 9-32 FEDACCTL1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-25	RESERVED	R	0h	Reserved
24	SUSP_IGNR	R/W	0h	Internal. Only to be used through TI provided API.
23-0	RESERVED	R	0h	Reserved

9.7.1.29 FEDACSTAT Register (Offset = 201Ch) [Reset = 00000000h]

FEDACSTAT is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FEDACSTAT_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FEDACSTAT_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-37 FEDACSTAT Register

31	30	29	28	27	26	25	24
RESERVED						RVF_INT	FSM_DONE
R-0h						R/W1C-0h	R/W1C-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED
R-0h

Table 9-33 FEDACSTAT Register Field Descriptions

Bit	Field	Type	Reset	Description
31-26	RESERVED	R	0h	Reserved
25	RVF_INT	R/W1C	0h	Internal. Only to be used through TI provided API.
24	FSM_DONE	R/W1C	0h	Internal. Only to be used through TI provided API.
23-0	RESERVED	R	0h	Reserved

9.7.1.30 FBPROT Register (Offset = 2030h) [Reset = 00000000h]

FBPROT is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FBPROT_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FBPROT_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-38 FBPROT Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED							PROTL1DIS
R-0h							R/W-0h

Table 9-34 FBPROT Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h	Reserved
0	PROTL1DIS	R/W	0h	Internal. Only to be used through TI provided API.

9.7.1.31 FBSE Register (Offset = 2034h) [Reset = 00000000h]

FBSE is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FBSE_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FBSE_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-39 FBSE Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																BSE
R-0h																R/W-0h

Table 9-35 FBSE Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h	Reserved
15-0	BSE	R/W	0h	Internal. Only to be used through TI provided API.

9.7.1.32 FBBUSY Register (Offset = 2038h) [Reset = 000000FCh]

FBBUSY is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FBBUSY_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FBBUSY_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-40 FBBUSY Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																								BUSY
R-0h																								R-FCh

Table 9-36 FBBUSY Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	RESERVED	R	0h	Reserved
7-0	BUSY	R	FCh	Internal. Only to be used through TI provided API.

9.7.1.33 FBAC Register (Offset = 203Ch) [Reset = 0000000Fh]

FBAC is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FBAC_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FBAC_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-41 FBAC Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED						OTPPROTDIS
R-0h						R/W-0h

15	14	13	12	11	10	9	8
BAGP
R/W-0h

7	6	5	4	3	2	1	0
VREADS
R/W-Fh

Table 9-37 FBAC Register Field Descriptions

Bit	Field	Type	Reset	Description
31-18	RESERVED	R	0h	Reserved
17-16	OTPPROTDIS	R/W	0h	Internal. Only to be used through TI provided API.
15-8	BAGP	R/W	0h	Internal. Only to be used through TI provided API.
7-0	VREADS	R/W	Fh	Internal. Only to be used through TI provided API.

9.7.1.34 FBFALLBACK Register (Offset = 2040h) [Reset = 0505FFFFh]

FBFALLBACK is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FBFALLBACK_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FBFALLBACK_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-42 FBFALLBACK Register

31	30	29	28	27	26	25	24
RESERVED				FSM_PWRSAV
R-0h				R/W-5h

23	22	21	20	19	18	17	16
RESERVED				REG_PWRSAV
R-0h				R/W-5h

15	14	13	12	11	10	9	8
BANKPWR7		BANKPWR6		BANKPWR5		BANKPWR4
R/W-3h		R/W-3h		R/W-3h		R/W-3h

7	6	5	4	3	2	1	0
BANKPWR3		BANKPWR2		BANKPWR1		BANKPWR0
R/W-3h		R/W-3h		R/W-3h		R/W-3h

Table 9-38 FBFALLBACK Register Field Descriptions

Bit	Field	Type	Reset	Description
31-28	RESERVED	R	0h	Reserved
27-24	FSM_PWRSAV	R/W	5h	Internal. Only to be used through TI provided API.
23-20	RESERVED	R	0h	Reserved
19-16	REG_PWRSAV	R/W	5h	Internal. Only to be used through TI provided API.
15-14	BANKPWR7	R/W	3h	Internal. Only to be used through TI provided API.
13-12	BANKPWR6	R/W	3h	Internal. Only to be used through TI provided API.
11-10	BANKPWR5	R/W	3h	Internal. Only to be used through TI provided API.
9-8	BANKPWR4	R/W	3h	Internal. Only to be used through TI provided API.
7-6	BANKPWR3	R/W	3h	Internal. Only to be used through TI provided API.
5-4	BANKPWR2	R/W	3h	Internal. Only to be used through TI provided API.
3-2	BANKPWR1	R/W	3h	Internal. Only to be used through TI provided API.
1-0	BANKPWR0	R/W	3h	Internal. Only to be used through TI provided API.

9.7.1.35 FBPRDY Register (Offset = 2044h) [Reset = 00FF00FCh]

FBPRDY is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FBPRDY_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FBPRDY_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-43 FBPRDY Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED						BANKBUSY
R-0h						R-3h

15	14	13	12	11	10	9	8
PUMPRDY	RESERVED
R-0h	R-0h

7	6	5	4	3	2	1	0
RESERVED						BANKRDY
R-0h						R-0h

Table 9-39 FBPRDY Register Field Descriptions

Bit	Field	Type	Reset	Description
31-18	RESERVED	R	0h	Reserved
17-16	BANKBUSY	R	3h	Internal. Only to be used through TI provided API.
15	PUMPRDY	R	0h	Internal. Only to be used through TI provided API.
14-2	RESERVED	R	0h	Reserved
1-0	BANKRDY	R	0h	Internal. Only to be used through TI provided API.

9.7.1.36 FPAC1 Register (Offset = 2048h) [Reset = 02082081h]

FPAC1 is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FPAC1_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FPAC1_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-44 FPAC1 Register

31	30	29	28	27	26	25	24
RESERVED				PSLEEPTDIS
R-0h				R/W-208h

23	22	21	20	19	18	17	16
PSLEEPTDIS
R/W-208h

15	14	13	12	11	10	9	8
PUMPRESET_PW
R/W-208h

7	6	5	4	3	2	1	0
PUMPRESET_PW				RESERVED		PUMPPWR
R/W-208h				R-0h		R/W-1h

Table 9-40 FPAC1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-28	RESERVED	R	0h	Reserved
27-16	PSLEEPTDIS	R/W	208h	Internal. Only to be used through TI provided API.
15-4	PUMPRESET_PW	R/W	208h	Internal. Only to be used through TI provided API.
3-2	RESERVED	R	0h	Reserved
1-0	PUMPPWR	R/W	1h	Internal. Only to be used through TI provided API.

9.7.1.37 FPAC2 Register (Offset = 204Ch) [Reset = 00000000h]

FPAC2 is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FPAC2_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FPAC2_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-45 FPAC2 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																PAGP
R-0h																R/W-0h

Table 9-41 FPAC2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h	Reserved
15-0	PAGP	R/W	0h	Internal. Only to be used through TI provided API.

9.7.1.38 FMAC Register (Offset = 2050h) [Reset = 00000000h]

FMAC is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FMAC_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FMAC_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-46 FMAC Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED													BANK
R-0h													R/W-0h

Table 9-42 FMAC Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2-0	BANK	R/W	0h	Internal. Only to be used through TI provided API.

9.7.1.39 FMSTAT Register (Offset = 2054h) [Reset = 00000000h]

FMSTAT is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FMSTAT_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FMSTAT_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-47 FMSTAT Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED						RVSUSP	RDVER
R-0h						R-0h	R-0h

15	14	13	12	11	10	9	8
RVF	ILA	DBF	PGV	PCV	EV	CV	BUSY
R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h

7	6	5	4	3	2	1	0
ERS	PGM	INVDAT	CSTAT	VOLSTAT	ESUSP	PSUSP	SLOCK
R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h	R-0h

Table 9-43 FMSTAT Register Field Descriptions

Bit	Field	Type	Reset	Description
31-18	RESERVED	R	0h	Reserved
17	RVSUSP	R	0h	Internal. Only to be used through TI provided API.
16	RDVER	R	0h	Internal. Only to be used through TI provided API.
15	RVF	R	0h	Internal. Only to be used through TI provided API.
14	ILA	R	0h	Internal. Only to be used through TI provided API.
13	DBF	R	0h	Internal. Only to be used through TI provided API.
12	PGV	R	0h	Internal. Only to be used through TI provided API.
11	PCV	R	0h	Internal. Only to be used through TI provided API.
10	EV	R	0h	Internal. Only to be used through TI provided API.
9	CV	R	0h	Internal. Only to be used through TI provided API.
8	BUSY	R	0h	Internal. Only to be used through TI provided API.
7	ERS	R	0h	Internal. Only to be used through TI provided API.
6	PGM	R	0h	Internal. Only to be used through TI provided API.
5	INVDAT	R	0h	Internal. Only to be used through TI provided API.
4	CSTAT	R	0h	Internal. Only to be used through TI provided API.
3	VOLSTAT	R	0h	Internal. Only to be used through TI provided API.
2	ESUSP	R	0h	Internal. Only to be used through TI provided API.
1	PSUSP	R	0h	Internal. Only to be used through TI provided API.
0	SLOCK	R	0h	Internal. Only to be used through TI provided API.

9.7.1.40 FLOCK Register (Offset = 2064h) [Reset = 000055AAh]

FLOCK is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FLOCK_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FLOCK_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-48 FLOCK Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																ENCOM
R-0h																R/W-55AAh

Table 9-44 FLOCK Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h	Reserved
15-0	ENCOM	R/W	55AAh	Internal. Only to be used through TI provided API.

9.7.1.41 FVREADCT Register (Offset = 2080h) [Reset = 00000008h]

FVREADCT is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FVREADCT_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FVREADCT_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-49 FVREADCT Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED												VREADCT
R-0h												R/W-8h

Table 9-45 FVREADCT Register Field Descriptions

Bit	Field	Type	Reset	Description
31-4	RESERVED	R	0h	Reserved
3-0	VREADCT	R/W	8h	Internal. Only to be used through TI provided API.

9.7.1.42 FVHVCT1 Register (Offset = 2084h) [Reset = 00840088h]

FVHVCT1 is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FVHVCT1_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FVHVCT1_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-50 FVHVCT1 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED								TRIM13_E				VHVCT_E
R-0h								R/W-8h				R/W-4h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED								TRIM13_PV				VHVCT_PV
R-0h								R/W-8h				R/W-8h

Table 9-46 FVHVCT1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RESERVED	R	0h	Reserved
23-20	TRIM13_E	R/W	8h	Internal. Only to be used through TI provided API.
19-16	VHVCT_E	R/W	4h	Internal. Only to be used through TI provided API.
15-8	RESERVED	R	0h	Reserved
7-4	TRIM13_PV	R/W	8h	Internal. Only to be used through TI provided API.
3-0	VHVCT_PV	R/W	8h	Internal. Only to be used through TI provided API.

9.7.1.43 FVHVCT2 Register (Offset = 2088h) [Reset = 00A20000h]

FVHVCT2 is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FVHVCT2_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FVHVCT2_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-51 FVHVCT2 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED								TRIM13_P				VHVCT_P
R-0h								R/W-Ah				R/W-2h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED
R-0h

Table 9-47 FVHVCT2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RESERVED	R	0h	Reserved
23-20	TRIM13_P	R/W	Ah	Internal. Only to be used through TI provided API.
19-16	VHVCT_P	R/W	2h	Internal. Only to be used through TI provided API.
15-0	RESERVED	R	0h	Reserved

9.7.1.44 FVHVCT3 Register (Offset = 208Ch) [Reset = 000F0000h]

FVHVCT3 is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FVHVCT3_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FVHVCT3_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-52 FVHVCT3 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED												WCT
R-0h												R/W-Fh

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED												VHVCT_READ
R-0h												R/W-0h

Table 9-48 FVHVCT3 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-20	RESERVED	R	0h	Reserved
19-16	WCT	R/W	Fh	Internal. Only to be used through TI provided API.
15-4	RESERVED	R	0h	Reserved
3-0	VHVCT_READ	R/W	0h	Internal. Only to be used through TI provided API.

9.7.1.45 FVNVCT Register (Offset = 2090h) [Reset = 00000800h]

FVNVCT is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FVNVCT_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FVNVCT_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-53 FVNVCT Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED			VCG2P5CT					RESERVED			VIN_CT
R-0h			R/W-8h					R-0h			R/W-0h

Table 9-49 FVNVCT Register Field Descriptions

Bit	Field	Type	Reset	Description
31-13	RESERVED	R	0h	Reserved
12-8	VCG2P5CT	R/W	8h	Internal. Only to be used through TI provided API.
7-5	RESERVED	R	0h	Reserved
4-0	VIN_CT	R/W	0h	Internal. Only to be used through TI provided API.

9.7.1.46 FVSLP Register (Offset = 2094h) [Reset = 00008000h]

FVSLP is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FVSLP_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FVSLP_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-54 FVSLP Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
VSL_P				RESERVED
R/W-8h				R-0h

Table 9-50 FVSLP Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h	Reserved
15-12	VSL_P	R/W	8h	Internal. Only to be used through TI provided API.
11-0	RESERVED	R	0h	Reserved

9.7.1.47 FVWLCT Register (Offset = 2098h) [Reset = 00000008h]

FVWLCT is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FVWLCT_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FVWLCT_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-55 FVWLCT Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED											VWLCT_P
R-0h											R/W-8h

Table 9-51 FVWLCT Register Field Descriptions

Bit	Field	Type	Reset	Description
31-5	RESERVED	R	0h	Reserved
4-0	VWLCT_P	R/W	8h	Internal. Only to be used through TI provided API.

9.7.1.48 FEFUSECTL Register (Offset = 209Ch) [Reset = 0701010Ah]

FEFUSECTL is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FEFUSECTL_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FEFUSECTL_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-56 FEFUSECTL Register

31	30	29	28	27	26	25	24
RESERVED					CHAIN_SEL
R-0h					R/W-7h

23	22	21	20	19	18	17	16
RESERVED						WRITE_EN	BP_SEL
R-0h						R/W-0h	R/W-1h

15	14	13	12	11	10	9	8
RESERVED							EF_CLRZ
R-0h							R/W-1h

7	6	5	4	3	2	1	0
RESERVED			EF_TEST	EFUSE_EN
R-0h			R/W-0h	R/W-Ah

Table 9-52 FEFUSECTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-27	RESERVED	R	0h	Reserved
26-24	CHAIN_SEL	R/W	7h	Internal. Only to be used through TI provided API.
23-18	RESERVED	R	0h	Reserved
17	WRITE_EN	R/W	0h	Internal. Only to be used through TI provided API.
16	BP_SEL	R/W	1h	Internal. Only to be used through TI provided API.
15-9	RESERVED	R	0h	Reserved
8	EF_CLRZ	R/W	1h	Internal. Only to be used through TI provided API.
7-5	RESERVED	R	0h	Reserved
4	EF_TEST	R/W	0h	Internal. Only to be used through TI provided API.
3-0	EFUSE_EN	R/W	Ah	Internal. Only to be used through TI provided API.

9.7.1.49 FEFUSESTAT Register (Offset = 20A0h) [Reset = 00000000h]

FEFUSESTAT is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FEFUSESTAT_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FEFUSESTAT_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-57 FEFUSESTAT Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED							SHIFT_DONE
R-0h							R/W1C-0h

Table 9-53 FEFUSESTAT Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h	Reserved
0	SHIFT_DONE	R/W1C	0h	Internal. Only to be used through TI provided API.

9.7.1.50 FEFUSEDATA Register (Offset = 20A4h) [Reset = 00000000h]

FEFUSEDATA is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FEFUSEDATA_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FEFUSEDATA_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-58 FEFUSEDATA Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
FEFUSEDATA
R/W-0h

Table 9-54 FEFUSEDATA Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	FEFUSEDATA	R/W	0h	Internal. Only to be used through TI provided API.

9.7.1.51 FSEQPMP Register (Offset = 20A8h) [Reset = 85080000h]

FSEQPMP is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSEQPMP_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSEQPMP_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-59 FSEQPMP Register

31	30	29	28	27	26	25	24
RESERVED				TRIM_3P4
R/W-8h				R/W-5h

23	22	21	20	19	18	17	16
RESERVED		TRIM_1P7		TRIM_0P8
R-0h		R/W-0h		R/W-8h

15	14	13	12	11	10	9	8
RESERVED	VIN_AT_X			RESERVED			VIN_BY_PASS
R-0h	R/W-0h			R-0h			R/W-0h

7	6	5	4	3	2	1	0
RESERVED
R-0h

Table 9-55 FSEQPMP Register Field Descriptions

Bit	Field	Type	Reset	Description
31-28	RESERVED	R/W	8h	Internal. Only to be used through TI provided API.
27-24	TRIM_3P4	R/W	5h	Internal. Only to be used through TI provided API.
23-22	RESERVED	R	0h	Reserved
21-20	TRIM_1P7	R/W	0h	Internal. Only to be used through TI provided API.
19-16	TRIM_0P8	R/W	8h	Internal. Only to be used through TI provided API.
15	RESERVED	R	0h	Reserved
14-12	VIN_AT_X	R/W	0h	Internal. Only to be used through TI provided API.
11-9	RESERVED	R	0h	Reserved
8	VIN_BY_PASS	R/W	0h	Internal. Only to be used through TI provided API.
7-0	RESERVED	R	0h	Reserved

9.7.1.52 FBSTROBES Register (Offset = 2100h) [Reset = 00000104h]

FBSTROBES is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FBSTROBES_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FBSTROBES_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-60 FBSTROBES Register

31	30	29	28	27	26	25	24
RESERVED							ECBIT
R-0h							R/W-0h

23	22	21	20	19	18	17	16
RESERVED					RWAIT2_FLCLK	RWAIT_FLCLK	FLCLKEN
R-0h					R/W-0h	R/W-0h	R/W-0h

15	14	13	12	11	10	9	8
RESERVED							CTRLENZ
R-0h							R/W-1h

7	6	5	4	3	2	1	0
RESERVED	NOCOLRED	PRECOL	TI_OTP	OTP	TEZ	RESERVED
R-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-1h	R-0h

Table 9-56 FBSTROBES Register Field Descriptions

Bit	Field	Type	Reset	Description
31-25	RESERVED	R	0h	Reserved
24	ECBIT	R/W	0h	Internal. Only to be used through TI provided API.
23-19	RESERVED	R	0h	Reserved
18	RWAIT2_FLCLK	R/W	0h	Internal. Only to be used through TI provided API.
17	RWAIT_FLCLK	R/W	0h	Internal. Only to be used through TI provided API.
16	FLCLKEN	R/W	0h	Internal. Only to be used through TI provided API.
15-9	RESERVED	R	0h	Reserved
8	CTRLENZ	R/W	1h	Internal. Only to be used through TI provided API.
7	RESERVED	R	0h	Reserved
6	NOCOLRED	R/W	0h	Internal. Only to be used through TI provided API.
5	PRECOL	R/W	0h	Internal. Only to be used through TI provided API.
4	TI_OTP	R/W	0h	Internal. Only to be used through TI provided API.
3	OTP	R/W	0h	Internal. Only to be used through TI provided API.
2	TEZ	R/W	1h	Internal. Only to be used through TI provided API.
1-0	RESERVED	R	0h	Reserved

9.7.1.53 FPSTROBES Register (Offset = 2104h) [Reset = 00000103h]

FPSTROBES is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FPSTROBES_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FPSTROBES_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-61 FPSTROBES Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED							EXECUTEZ
R-0h							R/W-1h

7	6	5	4	3	2	1	0
RESERVED						V3PWRDNZ	V5PWRDNZ
R-0h						R/W-1h	R/W-1h

Table 9-57 FPSTROBES Register Field Descriptions

Bit	Field	Type	Reset	Description
31-9	RESERVED	R	0h	Reserved
8	EXECUTEZ	R/W	1h	Internal. Only to be used through TI provided API.
7-2	RESERVED	R	0h	Reserved
1	V3PWRDNZ	R/W	1h	Internal. Only to be used through TI provided API.
0	V5PWRDNZ	R/W	1h	Internal. Only to be used through TI provided API.

9.7.1.54 FBMODE Register (Offset = 2108h) [Reset = 00000000h]

FBMODE is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FBMODE_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FBMODE_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-62 FBMODE Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED													MODE
R-0h													R/W-0h

Table 9-58 FBMODE Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2-0	MODE	R/W	0h	Internal. Only to be used through TI provided API.

9.7.1.55 FTCR Register (Offset = 210Ch) [Reset = 00000000h]

FTCR is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FTCR_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FTCR_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-63 FTCR Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																									TCR
R-0h																									R/W-0h

Table 9-59 FTCR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-7	RESERVED	R	0h	Reserved
6-0	TCR	R/W	0h	Internal. Only to be used through TI provided API.

9.7.1.56 FADDR Register (Offset = 2110h) [Reset = 00000000h]

FADDR is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FADDR_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FADDR_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-64 FADDR Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
FADDR
R/W-0h

Table 9-60 FADDR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	FADDR	R/W	0h	Internal. Only to be used through TI provided API.

9.7.1.57 FTCTL Register (Offset = 211Ch) [Reset = 00000000h]

FTCTL is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FTCTL_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FTCTL_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-65 FTCTL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED							WDATA_BLK_CLR
R-0h							R/W-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED						TEST_EN	RESERVED
R-0h						R/W-0h	R-0h

Table 9-61 FTCTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-17	RESERVED	R	0h	Reserved
16	WDATA_BLK_CLR	R/W	0h	Internal. Only to be used through TI provided API.
15-2	RESERVED	R	0h	Reserved
1	TEST_EN	R/W	0h	Internal. Only to be used through TI provided API.
0	RESERVED	R	0h	Reserved

9.7.1.58 FWPWRITE0 Register (Offset = 2120h) [Reset = FFFFFFFFh]

FWPWRITE0 is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FWPWRITE0_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FWPWRITE0_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-66 FWPWRITE0 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
FWPWRITE0
R/W-FFFFFFFFh

Table 9-62 FWPWRITE0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	FWPWRITE0	R/W	FFFFFFFFh	Internal. Only to be used through TI provided API.

9.7.1.59 FWPWRITE1 Register (Offset = 2124h) [Reset = FFFFFFFFh]

FWPWRITE1 is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FWPWRITE1_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FWPWRITE1_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-67 FWPWRITE1 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
FWPWRITE1
R/W-FFFFFFFFh

Table 9-63 FWPWRITE1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	FWPWRITE1	R/W	FFFFFFFFh	Internal. Only to be used through TI provided API.

9.7.1.60 FWPWRITE2 Register (Offset = 2128h) [Reset = FFFFFFFFh]

FWPWRITE2 is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FWPWRITE2_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FWPWRITE2_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-68 FWPWRITE2 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
FWPWRITE2
R/W-FFFFFFFFh

Table 9-64 FWPWRITE2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	FWPWRITE2	R/W	FFFFFFFFh	Internal. Only to be used through TI provided API.

9.7.1.61 FWPWRITE3 Register (Offset = 212Ch) [Reset = FFFFFFFFh]

FWPWRITE3 is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FWPWRITE3_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FWPWRITE3_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-69 FWPWRITE3 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
FWPWRITE3
R/W-FFFFFFFFh

Table 9-65 FWPWRITE3 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	FWPWRITE3	R/W	FFFFFFFFh	Internal. Only to be used through TI provided API.

9.7.1.62 FWPWRITE4 Register (Offset = 2130h) [Reset = FFFFFFFFh]

FWPWRITE4 is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FWPWRITE4_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FWPWRITE4_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-70 FWPWRITE4 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
FWPWRITE4
R/W-FFFFFFFFh

Table 9-66 FWPWRITE4 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	FWPWRITE4	R/W	FFFFFFFFh	Internal. Only to be used through TI provided API.

9.7.1.63 FWPWRITE5 Register (Offset = 2134h) [Reset = FFFFFFFFh]

FWPWRITE5 is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FWPWRITE5_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FWPWRITE5_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-71 FWPWRITE5 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
FWPWRITE5
R/W-FFFFFFFFh

Table 9-67 FWPWRITE5 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	FWPWRITE5	R/W	FFFFFFFFh	Internal. Only to be used through TI provided API.

9.7.1.64 FWPWRITE6 Register (Offset = 2138h) [Reset = FFFFFFFFh]

FWPWRITE6 is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FWPWRITE6_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FWPWRITE6_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-72 FWPWRITE6 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
FWPWRITE6
R/W-FFFFFFFFh

Table 9-68 FWPWRITE6 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	FWPWRITE6	R/W	FFFFFFFFh	Internal. Only to be used through TI provided API.

9.7.1.65 FWPWRITE7 Register (Offset = 213Ch) [Reset = FFFFFFFFh]

FWPWRITE7 is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FWPWRITE7_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FWPWRITE7_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-73 FWPWRITE7 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
FWPWRITE7
R/W-FFFFFFFFh

Table 9-69 FWPWRITE7 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	FWPWRITE7	R/W	FFFFFFFFh	Internal. Only to be used through TI provided API.

9.7.1.66 FWPWRITE_ECC Register (Offset = 2140h) [Reset = FFFFFFFFh]

FWPWRITE_ECC is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FWPWRITE_ECC_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FWPWRITE_ECC_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-74 FWPWRITE_ECC Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ECCBYTES07_00								ECCBYTES15_08
R/W-FFh								R/W-FFh

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ECCBYTES23_16								ECCBYTES31_24
R/W-FFh								R/W-FFh

Table 9-70 FWPWRITE_ECC Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	ECCBYTES07_00	R/W	FFh	Internal. Only to be used through TI provided API.
23-16	ECCBYTES15_08	R/W	FFh	Internal. Only to be used through TI provided API.
15-8	ECCBYTES23_16	R/W	FFh	Internal. Only to be used through TI provided API.
7-0	ECCBYTES31_24	R/W	FFh	Internal. Only to be used through TI provided API.

9.7.1.67 FSWSTAT Register (Offset = 2144h) [Reset = 00000001h]

FSWSTAT is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSWSTAT_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSWSTAT_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-75 FSWSTAT Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED							SAFELV
R-0h							R-1h

Table 9-71 FSWSTAT Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h	Reserved
0	SAFELV	R	1h	Internal. Only to be used through TI provided API.

9.7.1.68 FSM_GLBCTL Register (Offset = 2200h) [Reset = 00000001h]

FSM_GLBCTL is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_GLBCTL_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_GLBCTL_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-76 FSM_GLBCTL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED							CLKSEL
R-0h							R-1h

Table 9-72 FSM_GLBCTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h	Reserved
0	CLKSEL	R	1h	Internal. Only to be used through TI provided API.

9.7.1.69 FSM_STATE Register (Offset = 2204h) [Reset = 00000C00h]

FSM_STATE is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_STATE_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_STATE_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-77 FSM_STATE Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED				CTRLENZ	EXECUTEZ	RESERVED	FSM_ACT
R-0h				R-1h	R-1h	R-0h	R-0h

7	6	5	4	3	2	1	0
TIOTP_ACT	OTP_ACT	RESERVED
R-0h	R-0h	R-0h

Table 9-73 FSM_STATE Register Field Descriptions

Bit	Field	Type	Reset	Description
31-12	RESERVED	R	0h	Reserved
11	CTRLENZ	R	1h	Internal. Only to be used through TI provided API.
10	EXECUTEZ	R	1h	Internal. Only to be used through TI provided API.
9	RESERVED	R	0h	Reserved
8	FSM_ACT	R	0h	Internal. Only to be used through TI provided API.
7	TIOTP_ACT	R	0h	Internal. Only to be used through TI provided API.
6	OTP_ACT	R	0h	Internal. Only to be used through TI provided API.
5-0	RESERVED	R	0h	Reserved

9.7.1.70 FSM_STAT Register (Offset = 2208h) [Reset = 00000004h]

FSM_STAT is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_STAT_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_STAT_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-78 FSM_STAT Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED					NON_OP	OVR_PUL_CNT	INV_DAT
R-0h					R-1h	R-0h	R-0h

Table 9-74 FSM_STAT Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	NON_OP	R	1h	Internal. Only to be used through TI provided API.
1	OVR_PUL_CNT	R	0h	Internal. Only to be used through TI provided API.
0	INV_DAT	R	0h	Internal. Only to be used through TI provided API.

9.7.1.71 FSM_CMD Register (Offset = 220Ch) [Reset = 00000000h]

FSM_CMD is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_CMD_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_CMD_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-79 FSM_CMD Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																										FSMCMD
R-0h																										R/W-0h

Table 9-75 FSM_CMD Register Field Descriptions

Bit	Field	Type	Reset	Description
31-6	RESERVED	R	0h	Reserved
5-0	FSMCMD	R/W	0h	Internal. Only to be used through TI provided API.

9.7.1.72 FSM_PE_OSU Register (Offset = 2210h) [Reset = 00000000h]

FSM_PE_OSU is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_PE_OSU_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_PE_OSU_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-80 FSM_PE_OSU Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																PGM_OSU								ERA_OSU
R-0h																R/W-0h								R/W-0h

Table 9-76 FSM_PE_OSU Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h	Reserved
15-8	PGM_OSU	R/W	0h	Internal. Only to be used through TI provided API.
7-0	ERA_OSU	R/W	0h	Internal. Only to be used through TI provided API.

9.7.1.73 FSM_VSTAT Register (Offset = 2214h) [Reset = 00003000h]

FSM_VSTAT is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_VSTAT_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_VSTAT_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-81 FSM_VSTAT Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
VSTAT_CNT				RESERVED
R/W-3h				R-0h

Table 9-77 FSM_VSTAT Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h	Reserved
15-12	VSTAT_CNT	R/W	3h	Internal. Only to be used through TI provided API.
11-0	RESERVED	R	0h	Reserved

9.7.1.74 FSM_PE_VSU Register (Offset = 2218h) [Reset = 00000000h]

FSM_PE_VSU is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_PE_VSU_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_PE_VSU_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-82 FSM_PE_VSU Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																PGM_VSU								ERA_VSU
R-0h																R/W-0h								R/W-0h

Table 9-78 FSM_PE_VSU Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h	Reserved
15-8	PGM_VSU	R/W	0h	Internal. Only to be used through TI provided API.
7-0	ERA_VSU	R/W	0h	Internal. Only to be used through TI provided API.

9.7.1.75 FSM_CMP_VSU Register (Offset = 221Ch) [Reset = 00000000h]

FSM_CMP_VSU is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_CMP_VSU_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_CMP_VSU_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-83 FSM_CMP_VSU Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ADD_EXZ				RESERVED
R/W-0h				R-0h

Table 9-79 FSM_CMP_VSU Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h	Reserved
15-12	ADD_EXZ	R/W	0h	Internal. Only to be used through TI provided API.
11-0	RESERVED	R	0h	Reserved

9.7.1.76 FSM_EX_VAL Register (Offset = 2220h) [Reset = 00000301h]

FSM_EX_VAL is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_EX_VAL_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_EX_VAL_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-84 FSM_EX_VAL Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																REP_VSU								EXE_VALD
R-0h																R/W-3h								R/W-1h

Table 9-80 FSM_EX_VAL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h	Reserved
15-8	REP_VSU	R/W	3h	Internal. Only to be used through TI provided API.
7-0	EXE_VALD	R/W	1h	Internal. Only to be used through TI provided API.

9.7.1.77 FSM_RD_H Register (Offset = 2224h) [Reset = 0000005Ah]

FSM_RD_H is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_RD_H_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_RD_H_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-85 FSM_RD_H Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																								RD_H
R-0h																								R/W-5Ah

Table 9-81 FSM_RD_H Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	RESERVED	R	0h	Reserved
7-0	RD_H	R/W	5Ah	Internal. Only to be used through TI provided API.

9.7.1.78 FSM_P_OH Register (Offset = 2228h) [Reset = 00000100h]

FSM_P_OH is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_P_OH_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_P_OH_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-86 FSM_P_OH Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																PGM_OH								RESERVED
R-0h																R/W-1h								R-0h

Table 9-82 FSM_P_OH Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h	Reserved
15-8	PGM_OH	R/W	1h	Internal. Only to be used through TI provided API.
7-0	RESERVED	R	0h	Reserved

9.7.1.79 FSM_ERA_OH Register (Offset = 222Ch) [Reset = 00000001h]

FSM_ERA_OH is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_ERA_OH_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_ERA_OH_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-87 FSM_ERA_OH Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																ERA_OH
R-0h																R/W-1h

Table 9-83 FSM_ERA_OH Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h	Reserved
15-0	ERA_OH	R/W	1h	Internal. Only to be used through TI provided API.

9.7.1.80 FSM_SAV_PPUL Register (Offset = 2230h) [Reset = 00000000h]

FSM_SAV_PPUL is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_SAV_PPUL_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_SAV_PPUL_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-88 FSM_SAV_PPUL Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																				SAV_P_PUL
R-0h																				R-0h

Table 9-84 FSM_SAV_PPUL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-12	RESERVED	R	0h	Reserved
11-0	SAV_P_PUL	R	0h	Internal. Only to be used through TI provided API.

9.7.1.81 FSM_PE_VH Register (Offset = 2234h) [Reset = 00000100h]

FSM_PE_VH is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_PE_VH_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_PE_VH_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-89 FSM_PE_VH Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																PGM_VH								RESERVED
R-0h																R/W-1h								R-0h

Table 9-85 FSM_PE_VH Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h	Reserved
15-8	PGM_VH	R/W	1h	Internal. Only to be used through TI provided API.
7-0	RESERVED	R	0h	Reserved

9.7.1.82 FSM_PRG_PW Register (Offset = 2240h) [Reset = 00000000h]

FSM_PRG_PW is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_PRG_PW_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_PRG_PW_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-90 FSM_PRG_PW Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																PROG_PUL_WIDTH
R-0h																R/W-0h

Table 9-86 FSM_PRG_PW Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h	Reserved
15-0	PROG_PUL_WIDTH	R/W	0h	Internal. Only to be used through TI provided API.

9.7.1.83 FSM_ERA_PW Register (Offset = 2244h) [Reset = 00000000h]

FSM_ERA_PW is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_ERA_PW_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_ERA_PW_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-91 FSM_ERA_PW Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
FSM_ERA_PW
R/W-0h

Table 9-87 FSM_ERA_PW Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	FSM_ERA_PW	R/W	0h	Internal. Only to be used through TI provided API.

9.7.1.84 FSM_SAV_ERA_PUL Register (Offset = 2254h) [Reset = 00000000h]

FSM_SAV_ERA_PUL is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_SAV_ERA_PUL_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_SAV_ERA_PUL_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-92 FSM_SAV_ERA_PUL Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																				SAV_ERA_PUL
R-0h																				R-0h

Table 9-88 FSM_SAV_ERA_PUL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-12	RESERVED	R	0h	Internal. Only to be used through TI provided API.
11-0	SAV_ERA_PUL	R	0h	Internal. Only to be used through TI provided API.

9.7.1.85 FSM_TIMER Register (Offset = 2258h) [Reset = 00000000h]

FSM_TIMER is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_TIMER_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_TIMER_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-93 FSM_TIMER Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
FSM_TIMER
R-0h

Table 9-89 FSM_TIMER Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	FSM_TIMER	R	0h	Internal. Only to be used through TI provided API.

9.7.1.86 FSM_MODE Register (Offset = 225Ch) [Reset = 00000000h]

FSM_MODE is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_MODE_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_MODE_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-94 FSM_MODE Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED				RDV_SUBMODE		PGM_SUBMODE
R-0h				R-0h		R-0h

15	14	13	12	11	10	9	8
ERA_SUBMODE		SUBMODE		SAV_PGM_CMD			SAV_ERA_MODE
R-0h		R-0h		R-0h			R-0h

7	6	5	4	3	2	1	0
SAV_ERA_MODE		MODE			CMD
R-0h		R-0h			R-0h

Table 9-90 FSM_MODE Register Field Descriptions

Bit	Field	Type	Reset	Description
31-20	RESERVED	R	0h	Reserved
19-18	RDV_SUBMODE	R	0h	Internal. Only to be used through TI provided API.
17-16	PGM_SUBMODE	R	0h	Internal. Only to be used through TI provided API.
15-14	ERA_SUBMODE	R	0h	Internal. Only to be used through TI provided API.
13-12	SUBMODE	R	0h	Internal. Only to be used through TI provided API.
11-9	SAV_PGM_CMD	R	0h	Internal. Only to be used through TI provided API.
8-6	SAV_ERA_MODE	R	0h	Internal. Only to be used through TI provided API.
5-3	MODE	R	0h	Internal. Only to be used through TI provided API.
2-0	CMD	R	0h	Internal. Only to be used through TI provided API.

9.7.1.87 FSM_PGM Register (Offset = 2260h) [Reset = 00000000h]

FSM_PGM is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_PGM_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_PGM_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-95 FSM_PGM Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED						PGM_BANK			PGM_ADDR
R-0h						R-0h			R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PGM_ADDR
R-0h

Table 9-91 FSM_PGM Register Field Descriptions

Bit	Field	Type	Reset	Description
31-26	RESERVED	R	0h	Reserved
25-23	PGM_BANK	R	0h	Internal. Only to be used through TI provided API.
22-0	PGM_ADDR	R	0h	Internal. Only to be used through TI provided API.

9.7.1.88 FSM_ERA Register (Offset = 2264h) [Reset = 00000000h]

FSM_ERA is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_ERA_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_ERA_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-96 FSM_ERA Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED						ERA_BANK			ERA_ADDR
R-0h						R-0h			R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ERA_ADDR
R-0h

Table 9-92 FSM_ERA Register Field Descriptions

Bit	Field	Type	Reset	Description
31-26	RESERVED	R	0h	Reserved
25-23	ERA_BANK	R	0h	Internal. Only to be used through TI provided API.
22-0	ERA_ADDR	R	0h	Internal. Only to be used through TI provided API.

9.7.1.89 FSM_PRG_PUL Register (Offset = 2268h) [Reset = 00040032h]

FSM_PRG_PUL is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_PRG_PUL_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_PRG_PUL_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-97 FSM_PRG_PUL Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED												BEG_EC_LEVEL
R-0h												R/W-4h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED				MAX_PRG_PUL
R-0h				R/W-32h

Table 9-93 FSM_PRG_PUL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-20	RESERVED	R	0h	Reserved
19-16	BEG_EC_LEVEL	R/W	4h	Internal. Only to be used through TI provided API.
15-12	RESERVED	R	0h	Reserved
11-0	MAX_PRG_PUL	R/W	32h	Internal. Only to be used through TI provided API.

9.7.1.90 FSM_ERA_PUL Register (Offset = 226Ch) [Reset = 00040BB8h]

FSM_ERA_PUL is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_ERA_PUL_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_ERA_PUL_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-98 FSM_ERA_PUL Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED												MAX_EC_LEVEL
R-0h												R/W-4h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED				MAX_ERA_PUL
R-0h				R/W-BB8h

Table 9-94 FSM_ERA_PUL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-20	RESERVED	R	0h	Reserved
19-16	MAX_EC_LEVEL	R/W	4h	Internal. Only to be used through TI provided API.
15-12	RESERVED	R	0h	Reserved
11-0	MAX_ERA_PUL	R/W	BB8h	Internal. Only to be used through TI provided API.

9.7.1.91 FSM_STEP_SIZE Register (Offset = 2270h) [Reset = 00000000h]

FSM_STEP_SIZE is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_STEP_SIZE_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_STEP_SIZE_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-99 FSM_STEP_SIZE Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED							EC_STEP_SIZE
R-0h							R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED
R-0h

Table 9-95 FSM_STEP_SIZE Register Field Descriptions

Bit	Field	Type	Reset	Description
31-25	RESERVED	R	0h	Reserved
24-16	EC_STEP_SIZE	R/W	0h	Internal. Only to be used through TI provided API.
15-0	RESERVED	R	0h	Reserved

9.7.1.92 FSM_PUL_CNTR Register (Offset = 2274h) [Reset = 00000000h]

FSM_PUL_CNTR is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_PUL_CNTR_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_PUL_CNTR_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-100 FSM_PUL_CNTR Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED							CUR_EC_LEVEL
R-0h							R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED				PUL_CNTR
R-0h				R-0h

Table 9-96 FSM_PUL_CNTR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-25	RESERVED	R	0h	Reserved
24-16	CUR_EC_LEVEL	R	0h	Internal. Only to be used through TI provided API.
15-12	RESERVED	R	0h	Reserved
11-0	PUL_CNTR	R	0h	Internal. Only to be used through TI provided API.

9.7.1.93 FSM_EC_STEP_HEIGHT Register (Offset = 2278h) [Reset = 00000000h]

FSM_EC_STEP_HEIGHT is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_EC_STEP_HEIGHT_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_EC_STEP_HEIGHT_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-101 FSM_EC_STEP_HEIGHT Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED				EC_STEP_HEIGHT
R-0h				R/W-0h

Table 9-97 FSM_EC_STEP_HEIGHT Register Field Descriptions

Bit	Field	Type	Reset	Description
31-4	RESERVED	R	0h	Reserved
3-0	EC_STEP_HEIGHT	R/W	0h	Internal. Only to be used through TI provided API.

9.7.1.94 FSM_ST_MACHINE Register (Offset = 227Ch) [Reset = 00800500h]

FSM_ST_MACHINE is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_ST_MACHINE_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_ST_MACHINE_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-102 FSM_ST_MACHINE Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
DO_PRECOND	FSM_INT_EN	ALL_BANKS	CMPV_ALLOWED	RANDOM	RV_SEC_EN	RV_RES	RV_INT_EN
R/W-1h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

15	14	13	12	11	10	9	8
RESERVED	ONE_TIME_GOOD	RESERVED		DO_REDU_COL	DBG_SHORT_ROW
R-0h	R/W-0h	R-0h		R/W-0h	R/W-Ah

7	6	5	4	3	2	1	0
DBG_SHORT_ROW	RESERVED	PGM_SEC_COF_EN	PREC_STOP_EN	DIS_TST_EN	CMD_EN	INV_DATA	OVERRIDE
R/W-Ah	R-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

Table 9-98 FSM_ST_MACHINE Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RESERVED	R	0h	Reserved
23	DO_PRECOND	R/W	1h	Internal. Only to be used through TI provided API.
22	FSM_INT_EN	R/W	0h	Internal. Only to be used through TI provided API.
21	ALL_BANKS	R/W	0h	Internal. Only to be used through TI provided API.
20	CMPV_ALLOWED	R/W	0h	Internal. Only to be used through TI provided API.
19	RANDOM	R/W	0h	Internal. Only to be used through TI provided API.
18	RV_SEC_EN	R/W	0h	Internal. Only to be used through TI provided API.
17	RV_RES	R/W	0h	Internal. Only to be used through TI provided API.
16	RV_INT_EN	R/W	0h	Internal. Only to be used through TI provided API.
15	RESERVED	R	0h	Reserved
14	ONE_TIME_GOOD	R/W	0h	Internal. Only to be used through TI provided API.
13-12	RESERVED	R	0h	Reserved
11	DO_REDU_COL	R/W	0h	Internal. Only to be used through TI provided API.
10-7	DBG_SHORT_ROW	R/W	Ah	Internal. Only to be used through TI provided API.
6	RESERVED	R	0h	Reserved
5	PGM_SEC_COF_EN	R/W	0h	Internal. Only to be used through TI provided API.
4	PREC_STOP_EN	R/W	0h	Internal. Only to be used through TI provided API.
3	DIS_TST_EN	R/W	0h	Internal. Only to be used through TI provided API.
2	CMD_EN	R/W	0h	Internal. Only to be used through TI provided API.
1	INV_DATA	R/W	0h	Internal. Only to be used through TI provided API.
0	OVERRIDE	R/W	0h	Internal. Only to be used through TI provided API.

9.7.1.95 FSM_FLES Register (Offset = 2280h) [Reset = 00000000h]

FSM_FLES is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_FLES_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_FLES_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-103 FSM_FLES Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED				BLK_TIOTP				BLK_OTP
R-0h				R/W-0h				R/W-0h

Table 9-99 FSM_FLES Register Field Descriptions

Bit	Field	Type	Reset	Description
31-12	RESERVED	R	0h	Reserved
11-8	BLK_TIOTP	R/W	0h	Internal. Only to be used through TI provided API.
7-0	BLK_OTP	R/W	0h	Internal. Only to be used through TI provided API.

9.7.1.96 FSM_WR_ENA Register (Offset = 2288h) [Reset = 00000002h]

FSM_WR_ENA is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_WR_ENA_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_WR_ENA_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-104 FSM_WR_ENA Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED													WR_ENA
R-0h													R/W-2h

Table 9-100 FSM_WR_ENA Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2-0	WR_ENA	R/W	2h	Internal. Only to be used through TI provided API.

9.7.1.97 FSM_ACC_PP Register (Offset = 228Ch) [Reset = 00000000h]

FSM_ACC_PP is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_ACC_PP_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_ACC_PP_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-105 FSM_ACC_PP Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
FSM_ACC_PP
R-0h

Table 9-101 FSM_ACC_PP Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	FSM_ACC_PP	R	0h	Internal. Only to be used through TI provided API.

9.7.1.98 FSM_ACC_EP Register (Offset = 2290h) [Reset = 00000000h]

FSM_ACC_EP is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_ACC_EP_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_ACC_EP_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-106 FSM_ACC_EP Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																ACC_EP
R-0h																R-0h

Table 9-102 FSM_ACC_EP Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h	Reserved
15-0	ACC_EP	R	0h	Internal. Only to be used through TI provided API.

9.7.1.99 FSM_ADDR Register (Offset = 22A0h) [Reset = 00000000h]

FSM_ADDR is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_ADDR_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_ADDR_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-107 FSM_ADDR Register

31	30	29	28	27	26	25	24
RESERVED	BANK			CUR_ADDR
R-0h	R-0h			R-0h

23	22	21	20	19	18	17	16
CUR_ADDR
R-0h

15	14	13	12	11	10	9	8
CUR_ADDR
R-0h

7	6	5	4	3	2	1	0
CUR_ADDR
R-0h

Table 9-103 FSM_ADDR Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESERVED	R	0h	Reserved
30-28	BANK	R	0h	Internal. Only to be used through TI provided API.
27-0	CUR_ADDR	R	0h	Internal. Only to be used through TI provided API.

9.7.1.100 FSM_SECTOR Register (Offset = 22A4h) [Reset = FFFF0000h]

FSM_SECTOR is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_SECTOR_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_SECTOR_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-108 FSM_SECTOR Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SECT_ERASED
R/W-FFFFh

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
FSM_SECTOR_EXTENSION								SECTOR				SEC_OUT
R-0h								R-0h				R-0h

Table 9-104 FSM_SECTOR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	SECT_ERASED	R/W	FFFFh	Internal. Only to be used through TI provided API.
15-8	FSM_SECTOR_EXTENSION	R	0h	Internal. Only to be used through TI provided API.
7-4	SECTOR	R	0h	Internal. Only to be used through TI provided API.
3-0	SEC_OUT	R	0h	Internal. Only to be used through TI provided API.

9.7.1.101 FMC_REV_ID Register (Offset = 22A8h) [Reset = X]

FMC_REV_ID is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FMC_REV_ID_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FMC_REV_ID_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-109 FMC_REV_ID Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MOD_VERSION																				CONFIG_CRC
R-X																				R-X

Table 9-105 FMC_REV_ID Register Field Descriptions

Bit	Field	Type	Reset	Description
31-12	MOD_VERSION	R	X	Internal. Only to be used through TI provided API.
11-0	CONFIG_CRC	R	X	Internal. Only to be used through TI provided API.

9.7.1.102 FSM_ERR_ADDR Register (Offset = 22ACh) [Reset = 00000000h]

FSM_ERR_ADDR is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_ERR_ADDR_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_ERR_ADDR_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-110 FSM_ERR_ADDR Register

31	30	29	28	27	26	25	24
RESERVED	FSM_ERR_BANK			RESERVED
R-0h	R-0h			R-0h

23	22	21	20	19	18	17	16
FSM_ERR_ADDR
R-0h

15	14	13	12	11	10	9	8
FSM_ERR_ADDR
R-0h

7	6	5	4	3	2	1	0
FSM_ERR_ADDR
R-0h

Table 9-106 FSM_ERR_ADDR Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESERVED	R	0h	Reserved
30-28	FSM_ERR_BANK	R	0h	Internal. Only to be used through TI provided API.
27-24	RESERVED	R	0h	Reserved
23-0	FSM_ERR_ADDR	R	0h	Internal. Only to be used through TI provided API.

9.7.1.103 FSM_PGM_MAXPUL Register (Offset = 22B0h) [Reset = 00000000h]

FSM_PGM_MAXPUL is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_PGM_MAXPUL_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_PGM_MAXPUL_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-111 FSM_PGM_MAXPUL Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED				FSM_PGM_MAXPUL
R-0h				R-0h

Table 9-107 FSM_PGM_MAXPUL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-12	RESERVED	R	0h	Reserved
11-0	FSM_PGM_MAXPUL	R	0h	Internal. Only to be used through TI provided API.

9.7.1.104 FSM_EXECUTE Register (Offset = 22B4h) [Reset = 000A000Ah]

FSM_EXECUTE is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_EXECUTE_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_EXECUTE_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-112 FSM_EXECUTE Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED												SUSPEND_NOW
R-0h												R/W-Ah

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED											FSMEXECUTE
R-0h											R/W-Ah

Table 9-108 FSM_EXECUTE Register Field Descriptions

Bit	Field	Type	Reset	Description
31-20	RESERVED	R	0h	Reserved
19-16	SUSPEND_NOW	R/W	Ah	Internal. Only to be used through TI provided API.
15-5	RESERVED	R	0h	Reserved
4-0	FSMEXECUTE	R/W	Ah	Internal. Only to be used through TI provided API.

9.7.1.105 FSM_SECTOR1 Register (Offset = 22C0h) [Reset = FFFFFFFFh]

FSM_SECTOR1 is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_SECTOR1_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_SECTOR1_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-113 FSM_SECTOR1 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
FSM_SECTOR1
R/W-FFFFFFFFh

Table 9-109 FSM_SECTOR1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	FSM_SECTOR1	R/W	FFFFFFFFh	Internal. Only to be used through TI provided API.

9.7.1.106 FSM_SECTOR2 Register (Offset = 22C4h) [Reset = 00000FFFh]

FSM_SECTOR2 is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_SECTOR2_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_SECTOR2_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-114 FSM_SECTOR2 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
FSM_SECTOR2
R/W-FFFh

Table 9-110 FSM_SECTOR2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	FSM_SECTOR2	R/W	FFFh	Internal. Only to be used through TI provided API.

9.7.1.107 FSM_BSLE0 Register (Offset = 22E0h) [Reset = 00000000h]

FSM_BSLE0 is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_BSLE0_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_BSLE0_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-115 FSM_BSLE0 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
FSM_BSLE0
R/W-0h

Table 9-111 FSM_BSLE0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	FSM_BSLE0	R/W	0h	Internal. Only to be used through TI provided API.

9.7.1.108 FSM_BSLE1 Register (Offset = 22E4h) [Reset = 00000000h]

FSM_BSLE1 is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_BSLE1_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_BSLE1_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-116 FSM_BSLE1 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
FSM_BSLE1
R/W-0h

Table 9-112 FSM_BSLE1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	FSM_BSLE1	R/W	0h	Internal. Only to be used through TI provided API.

9.7.1.109 FSM_BSLP0 Register (Offset = 22F0h) [Reset = 00000000h]

FSM_BSLP0 is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_BSLP0_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_BSLP0_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-117 FSM_BSLP0 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
FSM_BSLP0
R/W-0h

Table 9-113 FSM_BSLP0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	FSM_BSLP0	R/W	0h	Internal. Only to be used through TI provided API.

9.7.1.110 FSM_BSLP1 Register (Offset = 22F4h) [Reset = 00000000h]

FSM_BSLP1 is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_BSLP1_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_BSLP1_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-118 FSM_BSLP1 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
FSM_BSLP1
R/W-0h

Table 9-114 FSM_BSLP1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	FSM_BSLP1	R/W	0h	Internal. Only to be used through TI provided API.

9.7.1.111 FSM_PGM128 Register (Offset = 22F8h) [Reset = 00000000h]

FSM_PGM128 is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_PGM128_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_PGM128_TABLE.

Return to the Summary Table.

FMC FSM Enable 128-bit Wide Programming

Figure 9-119 FSM_PGM128 Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED							EN_PGM128
R-0h							R/W-0h

Table 9-115 FSM_PGM128 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h	Reserved
0	EN_PGM128	R/W	0h	1: Enables 128-bit wide programming. This mode requires programming supply voltage to be greater than 2.5v at the Flash Pump. The primary use case for this mode is manufacturing test for test time reduction. 0: 64-bit wide programming. Valid at any programming voltage. A 128-bit word is divided into two 64-bit words for programming. [default] This register is write protected with the FSM_WR_ENA register.

9.7.1.112 FSM_EN_PRL_BNK_RD Register (Offset = 22FCh) [Reset = 00000000h]

FSM_EN_PRL_BNK_RD is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_EN_PRL_BNK_RD_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FSM_EN_PRL_BNK_RD_TABLE.

Return to the Summary Table.

FMC FSM Enable Parallell Reads for Multibanks

Figure 9-120 FSM_EN_PRL_BNK_RD Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED							EN_PRL_BNK_RD
R-0h							R/W-0h

Table 9-116 FSM_EN_PRL_BNK_RD Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h	Reserved
0	EN_PRL_BNK_RD	R/W	0h	1: Enables parallel reads of multiple banks The primary use case for this mode is manufacturing test for test time reduction. 0: Read of one bank only. [default] This register is write protected with the FSM_WR_ENA register.

9.7.1.113 FCFG_BANK Register (Offset = 2400h) [Reset = 00000802h]

FCFG_BANK is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_BANK_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_BANK_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-121 FCFG_BANK Register

31	30	29	28	27	26	25	24
EE_BANK_WIDTH
R-0h

23	22	21	20	19	18	17	16
EE_BANK_WIDTH				EE_NUM_BANK
R-0h				R-0h

15	14	13	12	11	10	9	8
MAIN_BANK_WIDTH
R-80h

7	6	5	4	3	2	1	0
MAIN_BANK_WIDTH				MAIN_NUM_BANK
R-80h				R-2h

Table 9-117 FCFG_BANK Register Field Descriptions

Bit	Field	Type	Reset	Description
31-20	EE_BANK_WIDTH	R	0h	Internal. Only to be used through TI provided API.
19-16	EE_NUM_BANK	R	0h	Internal. Only to be used through TI provided API.
15-4	MAIN_BANK_WIDTH	R	80h	Internal. Only to be used through TI provided API.
3-0	MAIN_NUM_BANK	R	2h	Internal. Only to be used through TI provided API.

9.7.1.114 FCFG_WRAPPER Register (Offset = 2404h) [Reset = 50009007h]

FCFG_WRAPPER is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_WRAPPER_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_WRAPPER_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-122 FCFG_WRAPPER Register

31	30	29	28	27	26	25	24
FAMILY_TYPE
R-50h

23	22	21	20	19	18	17	16
RESERVED			MEM_MAP	CPU2
R-0h			R-0h	R-0h

15	14	13	12	11	10	9	8
EE_IN_MAIN				ROM	IFLUSH	SIL3	ECCA
R-9h				R-0h	R-0h	R-0h	R-0h

7	6	5	4	3	2	1	0
AUTO_SUSP		UERR		CPU_TYPE1
R-0h		R-0h		R-7h

Table 9-118 FCFG_WRAPPER Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	FAMILY_TYPE	R	50h	Internal. Only to be used through TI provided API.
23-21	RESERVED	R	0h	Reserved
20	MEM_MAP	R	0h	Internal. Only to be used through TI provided API.
19-16	CPU2	R	0h	Internal. Only to be used through TI provided API.
15-12	EE_IN_MAIN	R	9h	Internal. Only to be used through TI provided API.
11	ROM	R	0h	Internal. Only to be used through TI provided API.
10	IFLUSH	R	0h	Internal. Only to be used through TI provided API.
9	SIL3	R	0h	Internal. Only to be used through TI provided API.
8	ECCA	R	0h	Internal. Only to be used through TI provided API.
7-6	AUTO_SUSP	R	0h	Internal. Only to be used through TI provided API.
5-4	UERR	R	0h	Internal. Only to be used through TI provided API.
3-0	CPU_TYPE1	R	7h	Internal. Only to be used through TI provided API.

9.7.1.115 FCFG_BNK_TYPE Register (Offset = 2408h) [Reset = 00000044h]

FCFG_BNK_TYPE is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_BNK_TYPE_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_BNK_TYPE_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-123 FCFG_BNK_TYPE Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
B7_TYPE				B6_TYPE				B5_TYPE				B4_TYPE
R-0h				R-0h				R-0h				R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
B3_TYPE				B2_TYPE				B1_TYPE				B0_TYPE
R-0h				R-0h				R-4h				R-4h

Table 9-119 FCFG_BNK_TYPE Register Field Descriptions

Bit	Field	Type	Reset	Description
31-28	B7_TYPE	R	0h	Internal. Only to be used through TI provided API.
27-24	B6_TYPE	R	0h	Internal. Only to be used through TI provided API.
23-20	B5_TYPE	R	0h	Internal. Only to be used through TI provided API.
19-16	B4_TYPE	R	0h	Internal. Only to be used through TI provided API.
15-12	B3_TYPE	R	0h	Internal. Only to be used through TI provided API.
11-8	B2_TYPE	R	0h	Internal. Only to be used through TI provided API.
7-4	B1_TYPE	R	4h	Internal. Only to be used through TI provided API.
3-0	B0_TYPE	R	4h	Internal. Only to be used through TI provided API.

9.7.1.116 FCFG_B0_START Register (Offset = 2410h) [Reset = 02000000h]

FCFG_B0_START is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B0_START_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B0_START_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-124 FCFG_B0_START Register

31	30	29	28	27	26	25	24
B0_MAX_SECTOR				B0_MUX_FACTOR
R-0h				R-2h

23	22	21	20	19	18	17	16
B0_START_ADDR
R-0h

15	14	13	12	11	10	9	8
B0_START_ADDR
R-0h

7	6	5	4	3	2	1	0
B0_START_ADDR
R-0h

Table 9-120 FCFG_B0_START Register Field Descriptions

Bit	Field	Type	Reset	Description
31-28	B0_MAX_SECTOR	R	0h	Internal. Only to be used through TI provided API.
27-24	B0_MUX_FACTOR	R	2h	Internal. Only to be used through TI provided API.
23-0	B0_START_ADDR	R	0h	Internal. Only to be used through TI provided API.

9.7.1.117 FCFG_B1_START Register (Offset = 2414h) [Reset = 02058000h]

FCFG_B1_START is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B1_START_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B1_START_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-125 FCFG_B1_START Register

31	30	29	28	27	26	25	24
B1_MAX_SECTOR				B1_MUX_FACTOR
R-0h				R-2h

23	22	21	20	19	18	17	16
B1_START_ADDR
R-00058000h

15	14	13	12	11	10	9	8
B1_START_ADDR
R-00058000h

7	6	5	4	3	2	1	0
B1_START_ADDR
R-00058000h

Table 9-121 FCFG_B1_START Register Field Descriptions

Bit	Field	Type	Reset	Description
31-28	B1_MAX_SECTOR	R	0h	Internal. Only to be used through TI provided API.
27-24	B1_MUX_FACTOR	R	2h	Internal. Only to be used through TI provided API.
23-0	B1_START_ADDR	R	00058000h	Internal. Only to be used through TI provided API.

9.7.1.118 FCFG_B2_START Register (Offset = 2418h) [Reset = 00000000h]

FCFG_B2_START is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B2_START_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B2_START_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-126 FCFG_B2_START Register

31	30	29	28	27	26	25	24
B2_MAX_SECTOR				B2_MUX_FACTOR
R-0h				R-0h

23	22	21	20	19	18	17	16
B2_START_ADDR
R-0h

15	14	13	12	11	10	9	8
B2_START_ADDR
R-0h

7	6	5	4	3	2	1	0
B2_START_ADDR
R-0h

Table 9-122 FCFG_B2_START Register Field Descriptions

Bit	Field	Type	Reset	Description
31-28	B2_MAX_SECTOR	R	0h	Internal. Only to be used through TI provided API.
27-24	B2_MUX_FACTOR	R	0h	Internal. Only to be used through TI provided API.
23-0	B2_START_ADDR	R	0h	Internal. Only to be used through TI provided API.

9.7.1.119 FCFG_B3_START Register (Offset = 241Ch) [Reset = 00000000h]

FCFG_B3_START is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B3_START_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B3_START_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-127 FCFG_B3_START Register

31	30	29	28	27	26	25	24
B3_MAX_SECTOR				B3_MUX_FACTOR
R-0h				R-0h

23	22	21	20	19	18	17	16
B3_START_ADDR
R-0h

15	14	13	12	11	10	9	8
B3_START_ADDR
R-0h

7	6	5	4	3	2	1	0
B3_START_ADDR
R-0h

Table 9-123 FCFG_B3_START Register Field Descriptions

Bit	Field	Type	Reset	Description
31-28	B3_MAX_SECTOR	R	0h	Internal. Only to be used through TI provided API.
27-24	B3_MUX_FACTOR	R	0h	Internal. Only to be used through TI provided API.
23-0	B3_START_ADDR	R	0h	Internal. Only to be used through TI provided API.

9.7.1.120 FCFG_B4_START Register (Offset = 2420h) [Reset = 00000000h]

FCFG_B4_START is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B4_START_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B4_START_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-128 FCFG_B4_START Register

31	30	29	28	27	26	25	24
B4_MAX_SECTOR				B4_MUX_FACTOR
R-0h				R-0h

23	22	21	20	19	18	17	16
B4_START_ADDR
R-0h

15	14	13	12	11	10	9	8
B4_START_ADDR
R-0h

7	6	5	4	3	2	1	0
B4_START_ADDR
R-0h

Table 9-124 FCFG_B4_START Register Field Descriptions

Bit	Field	Type	Reset	Description
31-28	B4_MAX_SECTOR	R	0h	Internal. Only to be used through TI provided API.
27-24	B4_MUX_FACTOR	R	0h	Internal. Only to be used through TI provided API.
23-0	B4_START_ADDR	R	0h	Internal. Only to be used through TI provided API.

9.7.1.121 FCFG_B5_START Register (Offset = 2424h) [Reset = 00000000h]

FCFG_B5_START is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B5_START_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B5_START_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-129 FCFG_B5_START Register

31	30	29	28	27	26	25	24
B5_MAX_SECTOR				B5_MUX_FACTOR
R-0h				R-0h

23	22	21	20	19	18	17	16
B5_START_ADDR
R-0h

15	14	13	12	11	10	9	8
B5_START_ADDR
R-0h

7	6	5	4	3	2	1	0
B5_START_ADDR
R-0h

Table 9-125 FCFG_B5_START Register Field Descriptions

Bit	Field	Type	Reset	Description
31-28	B5_MAX_SECTOR	R	0h	Internal. Only to be used through TI provided API.
27-24	B5_MUX_FACTOR	R	0h	Internal. Only to be used through TI provided API.
23-0	B5_START_ADDR	R	0h	Internal. Only to be used through TI provided API.

9.7.1.122 FCFG_B6_START Register (Offset = 2428h) [Reset = 00000000h]

FCFG_B6_START is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B6_START_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B6_START_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-130 FCFG_B6_START Register

31	30	29	28	27	26	25	24
B6_MAX_SECTOR				B6_MUX_FACTOR
R-0h				R-0h

23	22	21	20	19	18	17	16
B6_START_ADDR
R-0h

15	14	13	12	11	10	9	8
B6_START_ADDR
R-0h

7	6	5	4	3	2	1	0
B6_START_ADDR
R-0h

Table 9-126 FCFG_B6_START Register Field Descriptions

Bit	Field	Type	Reset	Description
31-28	B6_MAX_SECTOR	R	0h	Internal. Only to be used through TI provided API.
27-24	B6_MUX_FACTOR	R	0h	Internal. Only to be used through TI provided API.
23-0	B6_START_ADDR	R	0h	Internal. Only to be used through TI provided API.

9.7.1.123 FCFG_B7_START Register (Offset = 242Ch) [Reset = 00000000h]

FCFG_B7_START is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B7_START_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B7_START_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-131 FCFG_B7_START Register

31	30	29	28	27	26	25	24
B7_MAX_SECTOR				B7_MUX_FACTOR
R-0h				R-0h

23	22	21	20	19	18	17	16
B7_START_ADDR
R-0h

15	14	13	12	11	10	9	8
B7_START_ADDR
R-0h

7	6	5	4	3	2	1	0
B7_START_ADDR
R-0h

Table 9-127 FCFG_B7_START Register Field Descriptions

Bit	Field	Type	Reset	Description
31-28	B7_MAX_SECTOR	R	0h	Internal. Only to be used through TI provided API.
27-24	B7_MUX_FACTOR	R	0h	Internal. Only to be used through TI provided API.
23-0	B7_START_ADDR	R	0h	Internal. Only to be used through TI provided API.

9.7.1.124 FCFG_B0_SSIZE0 Register (Offset = 2430h) [Reset = 002C0008h]

FCFG_B0_SSIZE0 is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B0_SSIZE0_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B0_SSIZE0_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-132 FCFG_B0_SSIZE0 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED				B0_NUM_SECTORS
R-0h				R-2Ch

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED												B0_SECT_SIZE
R-0h												R-8h

Table 9-128 FCFG_B0_SSIZE0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-28	RESERVED	R	0h	Reserved
27-16	B0_NUM_SECTORS	R	2Ch	Internal. Only to be used through TI provided API.
15-4	RESERVED	R	0h	Reserved
3-0	B0_SECT_SIZE	R	8h	Internal. Only to be used through TI provided API.

9.7.1.125 FCFG_B0_SSIZE1 Register (Offset = 2434h) [Reset = 00000000h]

FCFG_B0_SSIZE1 is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B0_SSIZE1_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B0_SSIZE1_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-133 FCFG_B0_SSIZE1 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED
R-0h

Table 9-129 FCFG_B0_SSIZE1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	RESERVED	R	0h	Reserved

9.7.1.126 FCFG_B0_SSIZE2 Register (Offset = 2438h) [Reset = 00000000h]

FCFG_B0_SSIZE2 is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B0_SSIZE2_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B0_SSIZE2_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-134 FCFG_B0_SSIZE2 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED
R-0h

Table 9-130 FCFG_B0_SSIZE2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	RESERVED	R	0h	Reserved

9.7.1.127 FCFG_B0_SSIZE3 Register (Offset = 243Ch) [Reset = 00000000h]

FCFG_B0_SSIZE3 is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B0_SSIZE3_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B0_SSIZE3_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-135 FCFG_B0_SSIZE3 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED
R-0h

Table 9-131 FCFG_B0_SSIZE3 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	RESERVED	R	0h	Reserved

9.7.1.128 FCFG_B1_SSIZE0 Register (Offset = 2440h) [Reset = 002C0008h]

FCFG_B1_SSIZE0 is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B1_SSIZE0_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B1_SSIZE0_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-136 FCFG_B1_SSIZE0 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED				B0_NUM_SECTORS
R-0h				R-2Ch

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED												B0_SECT_SIZE
R-0h												R-8h

Table 9-132 FCFG_B1_SSIZE0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-28	RESERVED	R	0h	Reserved
27-16	B0_NUM_SECTORS	R	2Ch	Internal. Only to be used through TI provided API.
15-4	RESERVED	R	0h	Reserved
3-0	B0_SECT_SIZE	R	8h	Internal. Only to be used through TI provided API.

9.7.1.129 FCFG_B1_SSIZE1 Register (Offset = 2444h) [Reset = 00000000h]

FCFG_B1_SSIZE1 is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B1_SSIZE1_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B1_SSIZE1_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-137 FCFG_B1_SSIZE1 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED
R-0h

Table 9-133 FCFG_B1_SSIZE1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	RESERVED	R	0h	Reserved

9.7.1.130 FCFG_B1_SSIZE2 Register (Offset = 2448h) [Reset = 00000000h]

FCFG_B1_SSIZE2 is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B1_SSIZE2_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B1_SSIZE2_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-138 FCFG_B1_SSIZE2 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED
R-0h

Table 9-134 FCFG_B1_SSIZE2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	RESERVED	R	0h	Reserved

9.7.1.131 FCFG_B1_SSIZE3 Register (Offset = 244Ch) [Reset = 00000000h]

FCFG_B1_SSIZE3 is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B1_SSIZE3_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B1_SSIZE3_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-139 FCFG_B1_SSIZE3 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED
R-0h

Table 9-135 FCFG_B1_SSIZE3 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	RESERVED	R	0h	Reserved

9.7.1.132 FCFG_B2_SSIZE0 Register (Offset = 2450h) [Reset = 00000000h]

FCFG_B2_SSIZE0 is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B2_SSIZE0_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B2_SSIZE0_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-140 FCFG_B2_SSIZE0 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED				B0_NUM_SECTORS
R-0h				R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED												B0_SECT_SIZE
R-0h												R-0h

Table 9-136 FCFG_B2_SSIZE0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-28	RESERVED	R	0h	Reserved
27-16	B0_NUM_SECTORS	R	0h	Internal. Only to be used through TI provided API.
15-4	RESERVED	R	0h	Reserved
3-0	B0_SECT_SIZE	R	0h	Internal. Only to be used through TI provided API.

9.7.1.133 FCFG_B2_SSIZE1 Register (Offset = 2454h) [Reset = 00000000h]

FCFG_B2_SSIZE1 is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B2_SSIZE1_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B2_SSIZE1_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-141 FCFG_B2_SSIZE1 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED
R-0h

Table 9-137 FCFG_B2_SSIZE1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	RESERVED	R	0h	Reserved

9.7.1.134 FCFG_B2_SSIZE2 Register (Offset = 2458h) [Reset = 00000000h]

FCFG_B2_SSIZE2 is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B2_SSIZE2_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B2_SSIZE2_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-142 FCFG_B2_SSIZE2 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED
R-0h

Table 9-138 FCFG_B2_SSIZE2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	RESERVED	R	0h	Reserved

9.7.1.135 FCFG_B2_SSIZE3 Register (Offset = 245Ch) [Reset = 00000000h]

FCFG_B2_SSIZE3 is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B2_SSIZE3_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B2_SSIZE3_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-143 FCFG_B2_SSIZE3 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED
R-0h

Table 9-139 FCFG_B2_SSIZE3 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	RESERVED	R	0h	Reserved

9.7.1.136 FCFG_B3_SSIZE0 Register (Offset = 2460h) [Reset = 00000000h]

FCFG_B3_SSIZE0 is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B3_SSIZE0_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B3_SSIZE0_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-144 FCFG_B3_SSIZE0 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED
R-0h

Table 9-140 FCFG_B3_SSIZE0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	RESERVED	R	0h	Reserved

9.7.1.137 FCFG_B3_SSIZE1 Register (Offset = 2464h) [Reset = 00000000h]

FCFG_B3_SSIZE1 is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B3_SSIZE1_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B3_SSIZE1_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-145 FCFG_B3_SSIZE1 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED
R-0h

Table 9-141 FCFG_B3_SSIZE1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	RESERVED	R	0h	Reserved

9.7.1.138 FCFG_B3_SSIZE2 Register (Offset = 2468h) [Reset = 00000000h]

FCFG_B3_SSIZE2 is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B3_SSIZE2_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B3_SSIZE2_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-146 FCFG_B3_SSIZE2 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED
R-0h

Table 9-142 FCFG_B3_SSIZE2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	RESERVED	R	0h	Reserved

9.7.1.139 FCFG_B3_SSIZE3 Register (Offset = 246Ch) [Reset = 00000000h]

FCFG_B3_SSIZE3 is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B3_SSIZE3_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B3_SSIZE3_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-147 FCFG_B3_SSIZE3 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED
R-0h

Table 9-143 FCFG_B3_SSIZE3 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	RESERVED	R	0h	Reserved

9.7.1.140 FCFG_B4_SSIZE0 Register (Offset = 2470h) [Reset = 00000000h]

FCFG_B4_SSIZE0 is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B4_SSIZE0_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B4_SSIZE0_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-148 FCFG_B4_SSIZE0 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED
R-0h

Table 9-144 FCFG_B4_SSIZE0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	RESERVED	R	0h	Reserved

9.7.1.141 FCFG_B4_SSIZE1 Register (Offset = 2474h) [Reset = 00000000h]

FCFG_B4_SSIZE1 is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B4_SSIZE1_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B4_SSIZE1_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-149 FCFG_B4_SSIZE1 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED
R-0h

Table 9-145 FCFG_B4_SSIZE1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	RESERVED	R	0h	Reserved

9.7.1.142 FCFG_B4_SSIZE2 Register (Offset = 2478h) [Reset = 00000000h]

FCFG_B4_SSIZE2 is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B4_SSIZE2_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B4_SSIZE2_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-150 FCFG_B4_SSIZE2 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED
R-0h

Table 9-146 FCFG_B4_SSIZE2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	RESERVED	R	0h	Reserved

9.7.1.143 FCFG_B4_SSIZE3 Register (Offset = 247Ch) [Reset = 00000000h]

FCFG_B4_SSIZE3 is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B4_SSIZE3_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B4_SSIZE3_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-151 FCFG_B4_SSIZE3 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED
R-0h

Table 9-147 FCFG_B4_SSIZE3 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	RESERVED	R	0h	Reserved

9.7.1.144 FCFG_B5_SSIZE0 Register (Offset = 2480h) [Reset = 00000000h]

FCFG_B5_SSIZE0 is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B5_SSIZE0_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B5_SSIZE0_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-152 FCFG_B5_SSIZE0 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED
R-0h

Table 9-148 FCFG_B5_SSIZE0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	RESERVED	R	0h	Reserved

9.7.1.145 FCFG_B5_SSIZE1 Register (Offset = 2484h) [Reset = 00000000h]

FCFG_B5_SSIZE1 is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B5_SSIZE1_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B5_SSIZE1_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-153 FCFG_B5_SSIZE1 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED
R-0h

Table 9-149 FCFG_B5_SSIZE1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	RESERVED	R	0h	Reserved

9.7.1.146 FCFG_B5_SSIZE2 Register (Offset = 2488h) [Reset = 00000000h]

FCFG_B5_SSIZE2 is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B5_SSIZE2_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B5_SSIZE2_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-154 FCFG_B5_SSIZE2 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED
R-0h

Table 9-150 FCFG_B5_SSIZE2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	RESERVED	R	0h	Reserved

9.7.1.147 FCFG_B5_SSIZE3 Register (Offset = 248Ch) [Reset = 00000000h]

FCFG_B5_SSIZE3 is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B5_SSIZE3_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B5_SSIZE3_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-155 FCFG_B5_SSIZE3 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED
R-0h

Table 9-151 FCFG_B5_SSIZE3 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	RESERVED	R	0h	Reserved

9.7.1.148 FCFG_B6_SSIZE0 Register (Offset = 2490h) [Reset = 00000000h]

FCFG_B6_SSIZE0 is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B6_SSIZE0_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B6_SSIZE0_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-156 FCFG_B6_SSIZE0 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED
R-0h

Table 9-152 FCFG_B6_SSIZE0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	RESERVED	R	0h	Reserved

9.7.1.149 FCFG_B6_SSIZE1 Register (Offset = 2494h) [Reset = 00000000h]

FCFG_B6_SSIZE1 is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B6_SSIZE1_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B6_SSIZE1_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-157 FCFG_B6_SSIZE1 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED
R-0h

Table 9-153 FCFG_B6_SSIZE1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	RESERVED	R	0h	Reserved

9.7.1.150 FCFG_B6_SSIZE2 Register (Offset = 2498h) [Reset = 00000000h]

FCFG_B6_SSIZE2 is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B6_SSIZE2_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B6_SSIZE2_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-158 FCFG_B6_SSIZE2 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED
R-0h

Table 9-154 FCFG_B6_SSIZE2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	RESERVED	R	0h	Reserved

9.7.1.151 FCFG_B6_SSIZE3 Register (Offset = 249Ch) [Reset = 00000000h]

FCFG_B6_SSIZE3 is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B6_SSIZE3_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B6_SSIZE3_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-159 FCFG_B6_SSIZE3 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED
R-0h

Table 9-155 FCFG_B6_SSIZE3 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	RESERVED	R	0h	Reserved

9.7.1.152 FCFG_B7_SSIZE0 Register (Offset = 24A0h) [Reset = 00000000h]

FCFG_B7_SSIZE0 is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B7_SSIZE0_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B7_SSIZE0_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-160 FCFG_B7_SSIZE0 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED
R-0h

Table 9-156 FCFG_B7_SSIZE0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	RESERVED	R	0h	Reserved

9.7.1.153 FCFG_B7_SSIZE1 Register (Offset = 24A4h) [Reset = 00000000h]

FCFG_B7_SSIZE1 is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B7_SSIZE1_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B7_SSIZE1_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-161 FCFG_B7_SSIZE1 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED
R-0h

Table 9-157 FCFG_B7_SSIZE1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	RESERVED	R	0h	Reserved

9.7.1.154 FCFG_B7_SSIZE2 Register (Offset = 24A8h) [Reset = 00000000h]

FCFG_B7_SSIZE2 is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B7_SSIZE2_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B7_SSIZE2_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-162 FCFG_B7_SSIZE2 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED
R-0h

Table 9-158 FCFG_B7_SSIZE2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	RESERVED	R	0h	Reserved

9.7.1.155 FCFG_B7_SSIZE3 Register (Offset = 24ACh) [Reset = 00000000h]

FCFG_B7_SSIZE3 is shown in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B7_SSIZE3_FIGURE and described in #FLASH_MMR_FLASH_MMR_MMAP2_FLASH_MMR_ALL_FCFG_B7_SSIZE3_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 9-163 FCFG_B7_SSIZE3 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED
R-0h

Table 9-159 FCFG_B7_SSIZE3 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	RESERVED	R	0h	Reserved